Samsung patents chip wiring design with uniform insulating barriers
This patent describes a specific layout for connecting components inside a computer chip. It uses vertical wiring lines surrounded by insulating material that keeps a consistent width to separate the electrical paths.
In the filing’s own words
An integrated circuit device includes a plurality of wiring structures on a substrate and extending in a first direction parallel to an upper surface of the substrate and each including a wiring layer on the substrate and extending in a direction perpendicular to the upper surface of the substrate; an insulating pattern surrounding a sidewall of the wiring layer and including a first insulating material; and a capping layer on an upper surface of the wiring layer and including a conductive material; a via layer on the wiring structures, the via layer being electrically connected to one wiring structure; and an interlayer insulating layer covering a sidewall of the insulating pattern between each wiring structure of the plurality of wiring structures, the interlayer insulating layer having an upper surface higher than an upper surface of each wiring layer and an upper surface of each insulating pattern.
What exactly they claim (claim 1)
1. An integrated circuit device, comprising: a front-end-of-line (FEOL) structure including a substrate, a plurality of integrated devices, and a lower insulating layer on the substrate; a plurality of wiring structures on the FEOL structure, the plurality of wiring structures extending in a first direction parallel to an upper surface of the substrate and each including: a wiring layer on an upper surface of the lower insulating layer and extending in a vertical direction, perpendicular to the upper surface of the substrate, from the upper surface of the lower insulating layer to an upper surface of the wiring layer; an insulating pattern surrounding a sidewall of the wiring layer and including a first insulating material, the insulating pattern including a portion extending continuously in the vertical direction from the upper surface of the lower insulating layer to an upper surface of the insulating pattern; and a capping layer on the upper surface of the wiring layer and including a conductive material; a via layer on and connected to a first wiring structure of the plurality of wiring structures; and an interlayer insulating layer covering a sidewall of the insulating pattern between each wiring structure of the plurality of wiring structures, the interlayer insulating layer having an upper surface higher than the upper surface of each wiring layer and the upper surface of each insulating pattern, wherein the portion of each insulating pattern has a constant width in a second direction perpendicular to the first direction and perpendicular to the vertical direction, and wherein each wiring layer has a constant width in the second direction.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- Integrated circuit device
- Patent number
- US12765363B2
- Application number
- 18219244
- Filed
- Jul 7, 2023
- Granted
- Oct 13, 2026
- Inventors
- 2
- Claims
- 20
Classified under
H10W 20/435 Electricity & electronicsH10W 20/035 Electricity & electronicsH10W 20/075 Electricity & electronicsH10W 20/076 Electricity & electronicsH10W 20/089 Electricity & electronicsH10W 20/42 Electricity & electronicsMore from Samsung in Chips & hardware
- Samsung patents chip that combines camera and screen Oct 13, 2026
- Samsung patents faster chip testing using machine learning Sep 1, 2026
- Samsung patents radar method to pinpoint target direction more accurately Sep 1, 2026
- Samsung patents memory chip that searches data by content, not address Sep 1, 2026
- Samsung patents chip design that skips empty data to speed up AI Sep 1, 2026
Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.