Samsung patents stacked chip design with vertical gate contacts
Samsung has been granted a patent for a semiconductor device that stacks two layers of chips to save space. The design uses vertical gate electrodes and specific contact plugs to connect the upper memory layer to the lower circuit layer.
In the filing’s own words
A semiconductor device includes a substrate including a first region and a second region; insulating patterns in the substrate; gate electrodes provided below the substrate and spaced apart from each other in a first direction that is perpendicular to a lower surface of the substrate, the gate electrodes including pad regions arranged in a step shape below the second region; gate contact plugs passing through the pad regions of the gate electrodes, extending in the first direction, and vertically overlapping the insulating patterns; and a peripheral contact plug provided in an outer area of the substrate and extending from a level lower than a level of a lowermost gate electrode of the gate electrodes to a level higher than the lower surface of the substrate; and conductive patterns including a first conductive pattern provided on and connected to the peripheral contact plug, and second conductive patterns provided on and connected to the substrate.
What exactly they claim (claim 1)
1. A semiconductor device comprising: a first semiconductor structure comprising a first substrate, circuit elements provided on the first substrate, and a lower interconnection structure connected to the circuit elements; and a second semiconductor structure provided on the first semiconductor structure and connected to the first semiconductor structure, wherein the second semiconductor structure comprises: a second substrate comprising a first region and a second region; insulating patterns provided in the second substrate; gate electrodes provided between the second substrate and the first semiconductor structure and spaced apart from each other in a first direction that is perpendicular to a lower surface of the second substrate; a channel structure provided below the first region of the second substrate, penetrating through the gate electrodes and extending in the first direction, the channel structure comprising a channel layer; gate contact plugs passing through the gate electrodes, extending in the first direction, extending into the insulating patterns respectively, and spaced apart from the second substrate by the insulating patterns; and a source contact plug connected to the second substrate and extending from a level lower than a lowermost gate electrode closest to the first semiconductor structure, among the gate electrodes, to at least an inside of the second substrate.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- Semiconductor devices and data storage systems including the same
- Patent number
- US12765362B2
- Application number
- 18121456
- Filed
- Mar 14, 2023
- Granted
- Oct 13, 2026
- Inventors
- 2
- Claims
- 20
Classified under
H10W 20/435 Electricity & electronicsH10B 41/27 Electricity & electronicsH10B 41/35 Electricity & electronicsH10B 41/40 Electricity & electronicsH10B 43/27 Electricity & electronicsH10B 43/35 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.