Samsung patents chip layout method to align tiny circuit lines
Samsung describes a manufacturing technique for creating integrated circuits with precise alignment between different conductive lines. The method uses temporary reference patterns and spacers to control how much a second line shifts relative to the first, ensuring specific geometric shapes are formed on the chip.
In the filing’s own words
An integrated circuit (IC) device includes a first conductive line in a closed curve defining a local area on a substrate. The first conductive line has a first end portion and a second end portion. A second conductive line is outside the local area. The second conductive line has a linear line portion along the closed curve and a bulging end portion along the closed curve. The bulging end portion protrudes from the linear line portion toward the first end portion of the first conductive line in the second lateral direction and protrudes further than the first end portion to the outside of the local area. A method of manufacturing an IC device includes forming a first reference pattern having a mandrel hole. A reference spacer is formed inside the mandrel hole. A second reference pattern is formed. The second reference pattern has a shift hole.
What exactly they claim (claim 1)
1. A method of manufacturing an integrated circuit device, the method comprising: forming a target layer on a substrate; forming a reference layer on the target layer; forming a first reference pattern by patterning the reference layer, the first reference pattern extending in a first lateral direction, the first reference pattern defining a mandrel hole having a first end portion with an end at a first point on a straight line that follows the first lateral direction; forming a reference spacer inside the mandrel hole, the reference spacer having an inner sidewall in contact with a sidewall of the first reference pattern; selecting one moving point from among a first moving point, a second moving point, and a third moving point, wherein the first moving point is forward in the first lateral direction from a reference line extending in a second lateral direction through the first point, the second moving point passes through the reference line, and the third moving point is backward in the first lateral direction from the reference line, wherein the second lateral direction is perpendicular to the first lateral direction; and forming a second reference pattern by patterning the first reference pattern, the second reference pattern extending parallel to the mandrel hole in the first lateral direction, the second reference pattern having a second end portion extending to the selected moving point, the second reference pattern defining a shift hole exposing the inner sidewall of the reference spacer.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- Integrated circuit device and method of manufacturing the same
- Patent number
- US12765361B2
- Application number
- 18615177
- Filed
- Mar 25, 2024
- Granted
- Oct 13, 2026
- Inventors
- 2
- Claims
- 20
Classified under
H10W 20/43 Electricity & electronicsH10P 50/73 Electricity & electronicsH10W 20/056 Electricity & electronicsH10W 20/081 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.