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Samsung patents chip design with metal rails running through silicon

This patent describes a semiconductor structure where a vertical metal column, or rail, passes through a silicon base layer to connect a transistor on top with a contact point on the bottom. The design uses specific metal and barrier layers to ensure the top and bottom metal parts touch directly without extra insulation at their meeting point.

Why it mattersThis is a detailed manufacturing technique for building computer chips, which helps engineers create smaller and more efficient electronic components.

In the filing’s own words

A semiconductor device includes a base layer including a silicon material. A field effect transistor is disposed on a first surface of the base layer. A first insulating interlayer covers the field effect transistor, A buried vertical rail passes through the first insulating interlayer and the base layer. The buried vertical rail includes a first metal pattern and a first barrier pattern surrounding a sidewall of the first metal pattern. A first lower insulating interlayer is on the second surface of the base layer. A lower contact plug passes through the first lower insulating interlayer and directly contacts a lower surface of the buried vertical rail. The lower contact plug includes a second metal pattern and a second barrier pattern surrounding a sidewall of the second metal pattern. A bottom surface of the first metal pattern and a top surface of the second metal pattern directly contact each other.

What exactly they claim (claim 1)

1. A semiconductor device, comprising: a base layer including a silicon material, the base layer including a first surface and a second surface opposite to the first surface in a vertical direction; a field effect transistor disposed on the first surface of the base layer; a first insulating interlayer covering the field effect transistor; a buried vertical rail passing through the first insulating interlayer and the base layer, the buried vertical rail including a first metal pattern having a sidewall and a first barrier metal pattern surrounding only the sidewall of the first metal pattern; an etch stop layer on the second surface of the base layer; a first lower insulating interlayer on the etch stop layer; and a lower contact plug passing through the first lower insulating interlayer and the etch stop layer and directly contacting a lower surface of the buried vertical rail, the lower contact plug including a second metal pattern having a sidewall and a second barrier metal pattern surrounding only the sidewall of the second metal pattern, wherein a bottom surface of the first metal pattern and a top surface of the second metal pattern directly contact each other, and wherein the first barrier metal pattern and the second barrier metal pattern are not disposed at an interface between the top surface of the second metal pattern and the bottom surface of the first metal pattern.

Facts

Company
Samsung (SAMSUNG ELECTRONICS CO., LTD.)
Official title
Semiconductor device and method for manufacturing the same
Patent number
US12765347B2
Application number
18220971
Filed
Jul 12, 2023
Granted
Oct 13, 2026
Inventors
6
Claims
17

Classified under

H10W 20/20 Electricity & electronicsH10D 30/024 Electricity & electronicsH10D 30/6211 Electricity & electronicsH10D 64/017 Electricity & electronics
Read the full filing (official PDF) ↗ Open in the Patent Tracker

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.