Samsung patents stacked image sensor design with three chip layers

1. An image sensor, comprising: a first semiconductor chip including a first semiconductor substrate having a pixel unit in which a plurality of pixels are arranged, a first wiring structure on the first semiconductor substrate and having a first wiring layer, and a first bonding pad exposed to one surface of the first wiring structure and connected to the first wiring layer; a second semiconductor chip including a second semiconductor substrate having a first surface on which at least a portion of a plurality of transistors of a pixel signal generator circuit are located and a second surface opposite to the first surface, a second wiring structure on the first surface of the second semiconductor substrate, the second wiring structure having one surface in contact with the one surface of the first wiring structure, the second wiring structure having a second wiring layer, a second upper bonding pad exposed to the one surface of the second wiring structure and bonded to the first bonding pad, and a via structure connected to the second wiring layer and extending to the second surface of the second semiconductor substrate, the via structure including a via plug, and an insulating liner surrounding a side surface of the via plug, wherein the via plug includes a protruding portion that is exposed axially and protruding from the insulating liner along a longitudinal axis of the via plug; a bonding layer including a bonding insulating layer on the second surface of the second semiconductor substrate, and a second lower bonding pad buried in the bonding insulating layer and exposed to one surface of the bonding insulating layer, wherein the via plug connects the second wiring layer to the second lower bonding pad, wherein the protruding portion of the via plug contacts the second lower bonding pad, such that the second lower bonding pad is connected to the via structure; and a third semiconductor chip including a third semiconductor substrate having one surface on which logic devices are located, a third wiring structure on the one surface of the third semiconductor substrate, the third wiring structure having a third wiring layer, the third wiring structure having one surface in contact with the one surface of the bonding insulating layer, and a third bonding pad connected to the third wiring layer and exposed to the one surface of the third wiring structure, the third bonding pad bonded to the second lower bonding pad.