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SamsungGranted patentChips & hardwareInterest 3/10

Samsung patents chip layout that routes signals around power lines

This patent describes a specific way to arrange tiny electronic components called standard cells on a chip. It places a wire that carries signals right at the edge of a row of cells, running parallel to the power lines that feed them. This setup allows the chip to connect cells together while keeping the power supply separate but close by.

Why it mattersIt is a routine improvement in chip design that helps engineers pack more components into a smaller space efficiently.

In the filing’s own words

An integrated circuit includes a first cell in a first row extending in a first direction, a first power line extending in the first direction in a power rail layer, and configured to provide a first supply voltage to the first cell, and a first pattern overlapping a first boundary of the first row, and extending in the first direction in a first wiring layer, wherein the first cell includes at least one pattern extending in the first direction in the first wiring layer, and at least one transistor between the power rail layer and the first wiring layer, and the first pattern is configured to receive an input signal or an output signal of the first cell.

What exactly they claim (claim 1)

1. An integrated circuit comprising: a first cell in a first row extending in a first direction; a first power line extending in the first direction in a power rail layer, the first power line being configured to provide a first supply voltage to the first cell; and a first pattern overlapping a first boundary of the first row and extending in the first direction in a first wiring layer, the first boundary extending in the first direction and the first wiring layer being over the power rail layer; wherein the first cell includes: at least one pattern extending in the first direction in the first wiring layer; and at least one transistor between the power rail layer and the first wiring layer such that the first wiring layer is at least partially over the at least one transistor and the power rail layer is at least partially under the at least one transistor, and wherein the first pattern is configured to receive a first input signal or a first output signal of the first cell.

Facts

Company
Samsung (Samsung Electronics Co., Ltd.)
Official title
Integrated circuit including standard cells and method of designing the same
Patent number
US12765070B2
Application number
18469627
Filed
Sep 19, 2023
Granted
Oct 13, 2026
Inventors
6
Claims
20

Classified under

H10D 89/10 Electricity & electronicsH10D 84/834 Electricity & electronicsH10D 84/859 Electricity & electronicsH10W 20/42 Electricity & electronicsH10W 20/43 Electricity & electronics

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.