Samsung patents chip package with built-in capacitors to save space
Samsung describes a method for building a capacitor directly into the base layer of a semiconductor package. This design places the passive component underneath the main chip, using specific layers of insulation and metal to connect the parts without taking up extra room on the surface.
In the filing’s own words
Disclosed is a semiconductor package including: a redistribution substrate; at least one passive device in the redistribution substrate, the passive device including a first terminal and a second terminal; and a semiconductor chip on a top surface of the redistribution substrate, the semiconductor chip vertically overlapping at least a portion of the passive device, wherein the redistribution substrate includes: a dielectric layer in contact with a first lateral surface, a second lateral surface opposite to the first lateral surface, and a bottom surface of the passive device; a lower conductive pattern on the first terminal; a lower seed pattern provided between the first terminal and the conductive pattern, and directly connected to the first terminal; a first upper conductive pattern on the second terminal and a first upper seed pattern provided between the second terminal and the first upper conductive pattern, and directly connected to the second terminal.
What exactly they claim (claim 1)
1. A method of fabricating a semiconductor package, comprising: forming a capacitor on a carrier substrate, wherein the capacitor comprises a first terminal on the carrier substrate, and a second terminal on the first terminal; forming a first redistribution pattern on the carrier substrate which is laterally spaced apart from the capacitor without being connected to the capacitor; forming, on the carrier substrate, a first dielectric layer covering the first redistribution pattern and the capacitor; forming, on the first dielectric layer, a second redistribution pattern penetrating the first dielectric layer, and connected with the first redistribution pattern and the second terminal of the capacitor; forming, on the first dielectric layer, a second dielectric layer covering the second redistribution pattern; forming, on the second dielectric layer, a third redistribution pattern; removing the carrier substrate; forming a third dielectric layer on a bottom surface of the first dielectric layer; forming, on a bottom surface of the third dielectric layer, a fourth redistribution pattern penetrating the third dielectric layer, and connected with the first redistribution pattern and the first terminal of the capacitor; mounting a semiconductor chip on the fourth redistribution pattern, wherein the first dielectric layer has undulation at a top surface thereof over the capacitor, and wherein the second dielectric layer, at a top surface thereof, has reduced undulation than the undulation of the first dielectric layer.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- Semiconductor package with redistribution substrate having embedded passive device
- Patent number
- US12765044B2
- Application number
- 18478056
- Filed
- Sep 29, 2023
- Granted
- Oct 13, 2026
- Inventors
- 3
- Claims
- 20
Classified under
H10D 84/212 Electricity & electronicsH10D 1/692 Electricity & electronicsH10W 20/495 Electricity & electronicsH10W 70/611 Electricity & electronicsH10W 70/65 Electricity & electronicsH10W 72/20 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.