Samsung patents chip contacts using mixed crystal structures for better performance
This patent describes a specific way to build the tiny electrical connections inside a computer chip. It uses a metal filler made of molybdenum, tungsten, or similar elements that contains two different crystal shapes, with one shape making up at least 60% of the material.
In the filing’s own words
A semiconductor device includes a substrate including an active pattern, a channel pattern and a source/drain pattern that are on the active pattern and connected to each other, and an active contact electrically connected to the source/drain pattern. The active contact includes a first barrier metal and a first filler metal on the first barrier metal, and the first barrier metal includes a metal nitride layer. The first filler metal includes at least one of molybdenum, tungsten, ruthenium, cobalt, or vanadium. The first filler metal includes a first crystalline region having a body-centered cubic (BCC) structure and a second crystalline region having a face-centered cubic (FCC) structure. A proportion of the first crystalline region in the first filler metal ranges from 60% to 99%.
What exactly they claim (claim 1)
1. A semiconductor device, comprising: a substrate including an active pattern; a channel pattern and a source/drain pattern that are on the active pattern and connected to each other; and an active contact electrically connected to the source/drain pattern, wherein the active contact comprises a first barrier metal and a first filler metal on the first barrier metal and an upper insulating pattern on the first filler metal and the first barrier metal, wherein the first barrier metal comprises a metal nitride layer, wherein the first filler metal comprises at least one of molybdenum, tungsten, ruthenium, cobalt, or vanadium, wherein the first filler metal comprises a first crystalline region having a body-centered cubic (BCC) structure and a second crystalline region having a face-centered cubic (FCC) structure, wherein the upper insulating pattern is in contact with upper surfaces of the first filler metal and the first barrier metal, wherein an upper surface of the upper insulating pattern is coplanar with an upper surface of a gate contact, wherein a top surface of a first insulating pattern is coplanar with an upper surface of a gate capping pattern, a second insulating pattern on the first insulating pattern cover the gate capping pattern and a top surface of a second insulating pattern is coplanar with the upper surface of the gate contact, and wherein a proportion of the first crystalline region in the first filler metal ranges from 60% to 99%.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- Semiconductor device and method of fabricating the same
- Patent number
- US12765035B2
- Application number
- 17821033
- Filed
- Aug 19, 2022
- Granted
- Oct 13, 2026
- Inventors
- 4
- Claims
- 20
Classified under
H10D 64/62 Electricity & electronicsH10D 30/014 Electricity & electronicsH10D 30/031 Electricity & electronicsH10D 30/43 Electricity & electronicsH10D 30/6729 Electricity & electronicsH10D 30/6735 Electricity & electronicsMore from Samsung in Chips & hardware
- Samsung patents chip that combines camera and screen Oct 13, 2026
- Samsung patents faster chip testing using machine learning Sep 1, 2026
- Samsung patents radar method to pinpoint target direction more accurately Sep 1, 2026
- Samsung patents memory chip that searches data by content, not address Sep 1, 2026
- Samsung patents chip design that skips empty data to speed up AI Sep 1, 2026
Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.