Samsung patents chip design with mixed-width connections for better space use

1. A semiconductor device comprising: an active region disposed on a substrate; first to fourth gate structures sequentially disposed in a first horizontal direction and intersecting the active region, each of the first to fourth gate structures including a gate electrode and a gate capping layer on an upper surface of the gate electrode and a gate spacer on a side surface of the gate electrode; first to third source/drain regions sequentially disposed in the first horizontal direction among the first to fourth gate structures; a first narrow source/drain contact, a first wide source/drain contact and a second narrow source/drain contact sequentially disposed in the first horizontal direction among the first to fourth gate structures, the first narrow source/drain contact contacting the first source/drain region, the first wide source/drain contact contacting the second source/drain region, and the second narrow source/drain contact contacting the third source/drain region, wherein respective widths of the first and second narrow source/drain contacts, in the first horizontal direction, at a first height level, are smaller than a width of the first wide source/drain contact, in the first horizontal direction, at the first height level; an interlayer insulating layer covering the first to fourth gate structures and the first to third source/drain regions; and a gate contact disposed on the first gate structure and electrically connected to the gate electrode of the first gate structure, wherein: the first gate structure and the second gate structure are spaced apart from each other in the first horizontal direction by a first distance, the second gate structure and the third gate structure are spaced apart from each other by a second distance greater than the first distance, and the third gate structure and the fourth gate structure are spaced apart from each other by a third distance smaller than the second distance, a lower end of the first narrow source/drain contact is disposed at a higher level than a lower end of the first wide source/drain contact, the interlayer insulating layer contacts an upper surface of the first narrow source/drain contact and an upper surface of the gate capping layer of the first gate structure, and the gate spacer of the first gate structure contacts a lower surface of the gate capping layer of the first gate structure.