Samsung patents stacked chip design with deeper electrical contacts
Samsung describes a semiconductor structure where multiple channel layers are stacked vertically on a chip. The design uses a multi-layer source/drain pattern with a specific recessed area that allows electrical contacts to reach deeper into the structure.
In the filing’s own words
A semiconductor device may include a substrate, a channel pattern on the substrate, a source/drain pattern, an interlayer insulating pattern on the source/drain pattern, and an active contact penetrating the interlayer insulating layer and being electrically connected to the source/drain pattern. The channel pattern may include a plurality of semiconductor patterns. The plurality of semiconductor patterns may be vertically stacked and spaced apart from each other. A lowermost one of the plurality of semiconductor patterns may be a first semiconductor pattern. The source/drain pattern may be connected to the plurality of semiconductor patterns. A level of a bottommost surface of the active contact may be lower than a top surface of the first semiconductor pattern.
What exactly they claim (claim 1)
1. A semiconductor device, comprising: a substrate; a channel pattern on the substrate, the channel pattern including a plurality of semiconductor patterns, the plurality of semiconductor patterns being vertically stacked and spaced apart from each other, and a lowermost one of the plurality of semiconductor patterns being a first semiconductor pattern, a source/drain pattern connected to the plurality of semiconductor patterns; an interlayer insulating layer on the source/drain pattern; an active contact penetrating the interlayer insulating layer and being electrically connected to the source/drain pattern, wherein the source/drain pattern includes a first layer connected to the plurality of semiconductor patterns and a second layer interposed between the first layer and the active contact, a level of a topmost surface of the second layer is lower than a level of a bottommost surface of the active contact, and the level of the bottommost surface of the active contact is lower than a level of a top surface of the first semiconductor pattern.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- Semiconductor device having vertically stacked channels connected to a multi-layer source/drain pattern with an active contact recessed therein
- Patent number
- US12765017B2
- Application number
- 18462851
- Filed
- Sep 7, 2023
- Granted
- Oct 13, 2026
- Inventors
- 1
- Claims
- 17
Classified under
H10D 62/151 Electricity & electronicsH10D 30/014 Electricity & electronicsH10D 30/43 Electricity & electronicsH10D 30/6713 Electricity & electronicsH10D 30/6735 Electricity & electronicsH10D 30/6757 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.