Samsung patents chip design with air gaps in transistor parts
Samsung has been granted a patent for a specific layout of integrated circuit components. The design features transistors with 'fin' shapes where the source and drain areas contain small pockets of air. This structure uses stacked semiconductor layers to manage how electricity flows through the chip.
In the filing’s own words
An integrated circuit device includes a plurality of fin-type active areas extending in a first horizontal direction on a substrate, a plurality of channel regions respectively on the plurality of fin-type active areas, a plurality of gate lines surrounding the plurality of channel regions on the plurality of fin-type active areas and extending in a second horizontal direction that crosses the first horizontal direction, and a plurality of source/drain regions respectively at positions adjacent to the plurality of gate lines on the plurality of fin-type active areas and respectively in contact with the plurality of channel regions, and the plurality of source/drain regions respectively include a plurality of semiconductor layers and at least one air gap located therein.
What exactly they claim (claim 1)
1. An integrated circuit device comprising: a plurality of fin-type active areas extending in a first horizontal direction on a substrate; a plurality of channel regions respectively on the plurality of fin-type active areas; a plurality of gate lines surrounding the plurality of channel regions on the plurality of fin-type active areas and extending in a second horizontal direction that crosses the first horizontal direction; and a plurality of source/drain regions each arranged at positions adjacent to at least one of the plurality of gate lines on a respective one of the plurality of fin-type active areas and in contact with at least one of the plurality of channel regions, wherein each of the plurality of source/drain regions has a bottom surface in contact with the respective one of the plurality of fin-type active areas, wherein the plurality of source/drain regions include a first source/drain region and a second source/drain region; wherein the plurality of source/drain regions respectively include a plurality of semiconductor layers and at least one air gap located therein, wherein the second source/drain region has a top most surface at a lower vertical level than a vertical level of the top surface of the first source/drain region, and does not include any air gap therein, and wherein the plurality of semiconductor layers include: a first semiconductor layer including a part in contact with the at least one of the plurality of channel regions and a part in contact with the respective one of the plurality of fin-type active areas; a second semiconductor layer on the first semiconductor layer; and a third semiconductor layer on the second semiconductor layer.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- Integrated circuit devices
- Patent number
- US12765015B2
- Application number
- 18140905
- Filed
- Apr 28, 2023
- Granted
- Oct 13, 2026
- Inventors
- 9
- Claims
- 19
Classified under
H10D 62/151 Electricity & electronicsH10D 30/014 Electricity & electronicsH10D 30/43 Electricity & electronicsH10D 30/6735 Electricity & electronicsH10D 62/116 Electricity & electronicsH10D 62/121 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.