Samsung patents transistor design with extra channels for better performance

1. A semiconductor device comprising: a lower interlayer insulating layer; first and second active patterns extended in a first horizontal direction on the lower interlayer insulating layer, wherein the second active pattern is spaced apart from the first active pattern in a second horizontal direction that is different from the first horizontal direction; a gate electrode extended in the second horizontal direction on the first and second active patterns; a first source region disposed on a first side of the gate electrode and disposed on the first active pattern; a second source region disposed on a second side of the gate electrode, which opposes the first side of the gate electrode in the first horizontal direction, and disposed on the first active pattern; a third source region disposed on the first side of the gate electrode and disposed on the second active pattern; a drain region disposed on the second side of the gate electrode and disposed on the second active pattern; a first contact extended on the first side of the gate electrode in the second horizontal direction, wherein the first contact is connected to each of the first and third source regions; a second contact extended on the second side of the gate electrode in the second horizontal direction, wherein the second contact is connected to the second source region; a third contact extended on the second side of the gate electrode in the second horizontal direction, wherein the third contact is spaced apart from the second contact in the second horizontal direction, and the third contact is connected to the drain region; a lower wiring layer disposed inside the lower interlayer insulating layer, wherein the lower wiring layer extends in the first horizontal direction between the first active pattern and the second active pattern, wherein at least a portion of the lower wiring layer protrudes from an upper surface of the lower interlayer insulating layer in a vertical direction below the first contact; and a through via disposed between the first source region and the third source region, wherein the through via connects the lower wiring layer with the first contact, wherein each of the second contact and the third contact is electrically insulated from the lower wiring layer between the second source region and the drain region.