Samsung patents 3D memory design that shrinks chip size
Samsung has secured a patent for a 3D non-volatile memory chip that uses a stepped arrangement of wiring to save space. The design stacks a control layer on top of the memory cells, using specific transistors to connect the internal layers to the main decoder.
In the filing’s own words
A non-volatile memory device includes a first semiconductor layer including a cell area having a memory cell array and a stair area adjacent to the cell area, and a second semiconductor layer stacked on the first semiconductor layer in a vertical direction and including a row decoder. The first semiconductor layer includes a plurality of word lines stacked in the vertical direction, a layer including at least one string select line stacked on the plurality of word lines, and a plurality of first pass transistors in the stair area and on the layer including the at least one string select line, where, in the stair area, the plurality of word lines have a stepped shape, and the plurality of first pass transistors electrically connect the plurality of word lines to the row decoder.
What exactly they claim (claim 1)
1. A non-volatile memory device comprising: a first semiconductor layer comprising a cell area that includes a memory cell array, and a stair area adjacent to the cell area; and a second semiconductor layer stacked on the first semiconductor layer in a vertical direction and comprising a row decoder, wherein the first semiconductor layer comprises: a plurality of word lines stacked in the vertical direction; a layer comprising at least one string select line stacked on the plurality of word lines; and a plurality of first pass transistors disposed in the stair area, wherein each of the plurality of first pass transistors comprises a gate and a vertical channel extending in the vertical direction, wherein the gate is at a same level as the at least one string select line relative to a substrate, wherein, in the stair area, the plurality of word lines have a stepped shape, and wherein the plurality of first pass transistors electrically connect the plurality of word lines to the row decoder.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- Three-dimensional non-volatile memory device with reduced chip size
- Patent number
- US12764975B2
- Application number
- 18366723
- Filed
- Aug 8, 2023
- Granted
- Oct 13, 2026
- Inventors
- 3
- Claims
- 18
Classified under
H10B 80/00 Electricity & electronicsH10B 43/27 Electricity & electronicsH10B 43/35 Electricity & electronicsH10W 90/00 Electricity & electronicsH10W 90/792 Electricity & electronicsMore from Samsung in Chips & hardware
- Samsung patents chip that combines camera and screen Oct 13, 2026
- Samsung patents faster chip testing using machine learning Sep 1, 2026
- Samsung patents radar method to pinpoint target direction more accurately Sep 1, 2026
- Samsung patents memory chip that searches data by content, not address Sep 1, 2026
- Samsung patents chip design that skips empty data to speed up AI Sep 1, 2026
Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.