Samsung patents 3D memory design with angled cuts for better connections
Samsung describes a 3D memory chip design where vertical channels are cut through stacked layers of memory cells. The filing details specific shapes for these cuts, including angled sides and a covering structure, to manage how electrical connections are made within the device.
In the filing’s own words
The present disclosure provides for apparatuses and systems including integrated circuit devices. In some embodiments, an integrated circuit device includes a semiconductor substrate including a memory cell area and a connection area, a gate stack including a plurality of word line gate layers and a plurality of insulating layers and having a step structure in the connection area, a word line cut region passing through the plurality of word line gate layers in the memory cell area and the connection area and extending in a third direction, a plurality of first channel structures disposed on the memory cell area, a string select line gate layer disposed on the gate stack in the memory cell area, a plurality of second channel structures passing through the string select line gate layer, and a string select line cut region passing through the string select line gate layer.
What exactly they claim (claim 1)
1. An integrated circuit device, comprising: a semiconductor substrate comprising a memory cell area and a connection area; a gate stack comprising a plurality of word lines and a plurality of insulating layers, the plurality of word lines and the plurality of insulating layers extending in a first direction of a main surface of the semiconductor substrate and being alternately stacked in a second direction perpendicular to the main surface of the semiconductor substrate; a word line cut region passing through the plurality of word lines in the memory cell area and the connection area and extending in a third direction; a plurality of first channel structures disposed on the memory cell area and each of the plurality of first channel structures extending in the second direction and passing through the gate stack in the second direction; at least one string select line disposed on the gate stack in the memory cell area; a plurality of second channel structures passing through the at least one string select line and each of the plurality of second channel structures extending in the second direction; and a string select line cut region passing through the at least one string select line and extending in the third direction, wherein a portion of the at least one string select line is disposed as a cover structure overlapping the word line cut region, wherein the word line cut region has a shape of which a first horizontal width decreases as a distance from the main surface of the semiconductor substrate decreases, and wherein the cover structure disposed on the word line cut region extends in the third direction and has a shape of which a second horizontal width increases as the distance from the main surface of the semiconductor substrate decreases.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- Three-dimensional memory device and enhanced electronic system
- Patent number
- US12764962B2
- Application number
- 18212323
- Filed
- Jun 21, 2023
- Granted
- Oct 13, 2026
- Inventors
- 3
- Claims
- 16
Classified under
H10B 43/35 Electricity & electronicsH10B 41/27 Electricity & electronicsH10B 41/35 Electricity & electronicsH10B 43/27 Electricity & electronicsH10B 80/00 Electricity & electronicsH10W 90/00 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.