Samsung patents 3D memory design with new gate contact layout
Samsung has been granted a patent for a three-dimensional semiconductor memory device that uses a specific arrangement of vertical structures and gate contacts. The design places a gate contact between dummy vertical structures to connect to one of the stacked gate electrodes within the memory stack.
In the filing’s own words
The present disclosure relates to three-dimensional (3D) semiconductor memory devices and electronic systems. An example 3D semiconductor memory device comprises a substrate that includes a cell array region and a connection region, a structure in which a plurality of dielectric layers and a plurality of gate electrodes are alternately stacked on the substrate, a plurality of dummy vertical structures that extend through the structure on the connection region, and a gate contact that extends through the structure on the connection region and is connected to one gate electrode of the plurality of gate electrodes. The gate contact is between the plurality of dummy vertical structures in a plan view. The gate contact includes a first portion and a plurality of second portions that extend between the plurality of dummy vertical structures.
What exactly they claim (claim 1)
1. A three-dimensional semiconductor memory device comprising: a substrate that includes a cell array region and a connection region; a stack structure in which a plurality of dielectric layers and a plurality of gate electrodes are alternately stacked on the substrate; a plurality of dummy vertical structures that extend through the stack structure on the connection region; and a gate contact that extends through the stack structure on the connection region, the gate contact being electrically connected to one gate electrode of the plurality of gate electrodes, wherein the gate contact is between the plurality of dummy vertical structures in a plan view, wherein the gate contact includes: a first portion; and a plurality of second portions, wherein each second portion of the plurality of second portions extends between two adjacent dummy vertical structures of the plurality of dummy vertical structures, wherein the stack structure extends in a first direction, and wherein a length of the plurality of dielectric layers is the same as a length of the plurality of gate electrodes in the first direction.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- Three-dimensional semiconductor memory device and electronic system including the same
- Patent number
- US12764958B2
- Application number
- 18605147
- Filed
- Mar 14, 2024
- Granted
- Oct 13, 2026
- Inventors
- 3
- Claims
- 18
Classified under
H10B 43/27 Electricity & electronicsH10B 41/27 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.