Samsung patents memory chip design to reduce signal interference
This patent describes a specific layout for a semiconductor memory cell, likely for 3D NAND flash storage. It uses layers of insulating materials with different electrical properties to shield the data storage area from neighboring cells. The design aims to keep electrical signals contained within each cell to prevent them from leaking into adjacent ones.
In the filing’s own words
A semiconductor device includes a conductive pattern, an insulating pattern, a channel film extending in a vertical direction inside a channel hole, a charge trap pattern between the conductive pattern and the channel film inside the channel hole, a tunneling dielectric film between the charge trap pattern and the channel film, and a blocking dielectric film extending between the conductive pattern and the charge trap pattern and between the insulating pattern and the tunneling dielectric film. The insulating pattern includes a first insulating pattern overlapping the conductive pattern in the vertical direction and a second insulating pattern protruding in the lateral direction from the first insulating pattern into the channel hole and toward the channel film. The first insulating pattern has a first dielectric constant, and the second insulating pattern has a second dielectric constant that is lower than the first dielectric constant.
What exactly they claim (claim 1)
1. A semiconductor device comprising: a conductive pattern on a substrate, the conductive pattern extending in a lateral direction parallel to a surface of the substrate; an insulating pattern on the substrate, the insulating pattern extending parallel to the conductive pattern in the lateral direction; a channel film extending in a vertical direction to the surface of the substrate inside a channel hole passing through the conductive pattern and the insulating pattern; a charge trap pattern between the conductive pattern and the channel film inside the channel hole; a tunneling dielectric film between the charge trap pattern and the channel film; and a blocking dielectric film extending in the vertical direction inside the channel hole between the conductive pattern and the charge trap pattern, and between the insulating pattern and the tunneling dielectric film, the blocking dielectric film having a portion extending in the lateral direction beyond the charge trap pattern, wherein the insulating pattern comprises a first insulating pattern overlapping the conductive pattern in the vertical direction and a second insulating pattern protruding in the lateral direction from the first insulating pattern into the channel hole and toward the channel film, the first insulating pattern having a first dielectric constant, and the second insulating pattern having a second dielectric constant that is lower than the first dielectric constant.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- Semiconductor device having reduced intercell interference and electronic system including the same
- Patent number
- US12764956B2
- Application number
- 18308262
- Filed
- Apr 27, 2023
- Granted
- Oct 13, 2026
- Inventors
- 6
- Claims
- 20
Classified under
H10B 43/27 Electricity & electronicsH10B 43/40 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.