Samsung patents memory chip design with layered gates and varied insulators

1. A semiconductor memory device comprising: a cell substrate including a cell array region, a first extension region, a second extension region, and a through region; a first mold structure including a plurality of first gate electrodes sequentially stacked on the cell substrate and stacked on the second extension region in a stepwise manner; a first interlayer insulating layer comprising a first material with a first impurity concentration extending conformally on the first gate electrodes on the second extension region and on the through region; a second interlayer insulating layer comprising the first material with a second impurity concentration on the first interlayer insulating layer; a second mold structure including a plurality of second gate electrodes sequentially stacked on the second interlayer insulating layer and stacked on the first extension region in the stepwise manner; a third interlayer insulating layer on the second gate electrodes; a fourth interlayer insulating layer comprising the first material with a fourth impurity concentration on the third interlayer insulating layer; a channel structure in the first mold structure and the second mold structure on the cell array region; a first cell contact structure in the first interlayer insulating layer and in the first mold structure on the second extension region; and a second cell contact structure in the first interlayer insulating layer, the first mold structure, the second mold structure, and the third interlayer insulating layer on the first extension region, wherein the first impurity concentration of the first interlayer insulating layer is different from the second impurity concentration of the second interlayer insulating layer, the third interlayer insulating layer comprises the first material with a third impurity concentration and extends conformally on the second gate electrodes on the first extension region, on the second extension region, and on the through region, and the third impurity concentration of the third interlayer insulating layer is different from the fourth impurity concentration of the fourth interlayer insulating layer.