Samsung patents chip design that matches insulating layers for better contact
This patent describes a layout for a semiconductor chip where the top layer covering the memory bits is made of the same material as the insulating layer used in the surrounding circuitry. By using the same material for both the upper bit line capping and the first peripheral interlayer insulating layer, the design creates a uniform surface for placing electrical connections. This specific arrangement helps ensure that contact plugs can be made consistently across different parts of the chip.
In the filing’s own words
An example semiconductor device includes a bit line structure and a bit line capping pattern that are stacked on a memory cell array region. The device further includes a peripheral gate structure including a peripheral gate dielectric layer, a peripheral gate electrode, and a peripheral gate capping pattern that are stacked on a peripheral circuit region. The device further includes a gate spacer on a side surface of the peripheral gate structure, a first peripheral interlayer insulating layer covering the peripheral gate structure and the gate spacer, and a first peripheral contact plug penetrating through the first peripheral interlayer insulating layer. The bit line capping pattern includes a lower bit line capping layer and an upper bit line capping layer that are stacked. A material of the upper bit line capping layer is same as a material of the first peripheral interlayer insulating layer.
What exactly they claim (claim 1)
1. A semiconductor device, comprising: a bit line structure and a bit line capping pattern that are stacked on a memory cell array region of a substrate; a peripheral gate structure on a peripheral circuit region of the substrate, the peripheral gate structure including a peripheral gate dielectric layer, a peripheral gate electrode on the peripheral gate dielectric layer, and a peripheral gate capping pattern on the peripheral gate electrode; a gate spacer on a side surface of the peripheral gate structure; a first peripheral interlayer insulating layer on the peripheral circuit region of the substrate, the first peripheral interlayer insulating layer covering the peripheral gate structure and the gate spacer; and a first peripheral contact plug penetrating through the first peripheral interlayer insulating layer, wherein the bit line capping pattern includes a lower bit line capping layer and an upper bit line capping layer that are stacked, wherein a material of the upper bit line capping layer is same as a material of the first peripheral interlayer insulating layer, wherein an upper end of the first peripheral interlayer insulating layer is disposed at a level higher than a level of an upper surface of the peripheral gate capping pattern, and wherein a lower end of the first peripheral interlayer insulating layer is disposed at a level lower than a level of a lower surface of the peripheral gate electrode.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- Semiconductor device
- Patent number
- US12764942B2
- Application number
- 18622473
- Filed
- Mar 29, 2024
- Granted
- Oct 13, 2026
- Inventors
- 3
- Claims
- 20
Classified under
H10B 12/482 Electricity & electronicsH10B 12/09 Electricity & electronicsH10B 12/50 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.