Samsung patents 3D memory design with new internal wiring layout
This patent describes a specific arrangement for 3D semiconductor memory, where vertical bit lines connect to horizontal semiconductor patterns. It details how word lines, selection lines, and source lines are positioned around these patterns to manage data flow. The design focuses on the physical geometry of the memory cells within the chip.
In the filing’s own words
A semiconductor device includes a first bit line extending in a first direction, a first semiconductor pattern extending in a second direction and including first and second ends opposite to each other, the first end of the first semiconductor pattern being in contact with the first bit line, a first word line on the first semiconductor pattern and extending in a third direction, a selection line adjacent to the second end of the first semiconductor pattern and parallel to the third direction, a second semiconductor pattern interposed between the selection line and the first semiconductor pattern and having first end and second ends opposite to each other, a second bit line extending in the first direction and in contact with the first end of the second semiconductor pattern, and a source line extending in the first direction and in contact with the second end of the second semiconductor pattern.
What exactly they claim (claim 1)
1. A three-dimensional semiconductor memory device comprising: a first bit line extending longitudinally in a first direction that is perpendicular to an upper surface of a substrate; a first semiconductor pattern extending longitudinally in a second direction parallel to the upper surface of the substrate and comprising a first end and a second end opposite to each other, the first end of the first semiconductor pattern being in contact with the first bit line; a first word line that is on a middle portion of the first semiconductor pattern in the second direction and extends longitudinally in a third direction crossing the second direction and parallel to the upper surface of the substrate; a selection line adjacent to the second end of the first semiconductor pattern and parallel to the third direction; a second semiconductor pattern that is between the selection line and the first semiconductor pattern and comprises a first end and a second end opposite to each other; a second bit line extending longitudinally in the first direction and being in contact with the first end of the second semiconductor pattern; and a source line extending longitudinally in the first direction and being in contact with the second end of the second semiconductor pattern.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- Three-dimensional semiconductor memory device
- Patent number
- US12764941B2
- Application number
- 18528854
- Filed
- Dec 5, 2023
- Granted
- Oct 13, 2026
- Inventors
- 4
- Claims
- 20
Classified under
H10B 12/482 Electricity & electronicsH10B 12/485 Electricity & electronicsH10B 12/488 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.