Samsung patents memory chip design using high-k dielectric material
Samsung has been granted a patent for a semiconductor memory device that uses a specific insulating layer between the active parts of the chip and the word lines. This insulating layer is made of a high-k dielectric material and is designed to sit at the same height as the word lines to improve the structure's layout.
In the filing’s own words
A semiconductor memory device includes a bit line, first and second word lines spaced apart from each other on the bit line, a back gate electrode between the first and second word lines, a first active pattern between the first word line and the back gate electrode, a second active pattern between the second word line and the back gate electrode, contact patterns connected to the first and second active patterns, respectively, and a first gate insulating pattern between the first active pattern and the first word line and between the second active pattern and the second word line. A top surface of the first gate insulating pattern is located at substantially a same height as top surfaces of the first and second word lines. The first gate insulating pattern includes a high-k dielectric material.
What exactly they claim (claim 1)
1. A semiconductor memory device comprising: a bit line extending in a first direction; a first word line and a second word line which extend in a second direction intersecting the first direction on the bit line, and the first word line and the second word line are spaced apart from each other in the first direction; a back gate electrode extending in the second direction between the first word line and the second word line; a first active pattern between the first word line and the back gate electrode; a second active pattern between the second word line and the back gate electrode; contact patterns connected to the first active pattern and the second active pattern, respectively; and a first gate insulating pattern between the first active pattern and the first word line and between the second active pattern and the second word line, wherein a top surface of the first gate insulating pattern is located at substantially a same height as a top surface of the first word line and a top surface of the second word line, and wherein the first gate insulating pattern includes a high-k dielectric material.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- Semiconductor memory device including gate insulating pattern including high-k dielectric material
- Patent number
- US12764931B2
- Application number
- 18480389
- Filed
- Oct 3, 2023
- Granted
- Oct 13, 2026
- Inventors
- 4
- Claims
- 20
Classified under
H10B 12/315 Electricity & electronicsH10B 12/05 Electricity & electronicsMore from Samsung in Chips & hardware
- Samsung patents chip that combines camera and screen Oct 13, 2026
- Samsung patents faster chip testing using machine learning Sep 1, 2026
- Samsung patents radar method to pinpoint target direction more accurately Sep 1, 2026
- Samsung patents memory chip that searches data by content, not address Sep 1, 2026
- Samsung patents chip design that skips empty data to speed up AI Sep 1, 2026
Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.