Samsung patents layered capacitor structure to reduce electrical leakage
Samsung describes a method for building integrated circuits that uses a specific layering technique to create capacitors. The process involves depositing a dielectric film with multiple layers, including a special bottom layer designed to prevent unwanted electrical current from leaking through the device.
In the filing’s own words
A method of manufacturing an integrated circuit device may include forming a plurality of lower electrodes above a substrate, forming a supporter configured to support the plurality of lower electrodes, forming a dielectric film on the plurality of lower electrodes and the supporter, and forming an upper electrode on the dielectric film. The dielectric film may include a lower leakage current prevention layer on an outer surface of each of the plurality of lower electrodes and an outer surface of the supporter, a first capacitor material layer on the lower leakage current prevention layer, an upper material layer on the first capacitor material layer, and a second capacitor material layer on the upper material layer.
What exactly they claim (claim 1)
1. A method of manufacturing an integrated circuit device, the method comprising: forming a plurality of lower electrodes above a substrate; forming a supporter configured to support the plurality of lower electrodes; forming a dielectric film on the plurality of lower electrodes and the supporter; and forming an upper electrode on the dielectric film, wherein the dielectric film includes a lower leakage current prevention layer on an outer surface of each of the plurality of lower electrodes and an outer surface of the supporter, a first capacitor material layer on the lower leakage current prevention layer, an upper material layer on the first capacitor material layer, and a second capacitor material layer on the upper material layer, wherein the lower leakage current prevention layer includes a dielectric material doped with impurities, and the impurities include at least one of aluminum (Al), silicon (Si), magnesium (Mg), calcium (Ca), cobalt (Co), yttrium (Y), tantalum (Ta), niobium (Nb), hafnium (Hf), zirconium (Zr), and molybdenum (Mo), the forming the lower leakage current prevention layer includes alternately performing a first atomic layer deposition process and a second atomic layer deposition process, the first atomic layer deposition process includes a cycle of supplying and purging a dielectric film precursor, supplying and purging an impurity precursor, and supplying and purging a reactant, and the second atomic layer deposition process includes a cycle of supplying and purging the dielectric film precursor and supplying and purging the reactant.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- Integrated circuit device and method of manufacturing the same
- Patent number
- US12764930B2
- Application number
- 18333084
- Filed
- Jun 12, 2023
- Granted
- Oct 13, 2026
- Inventors
- 6
- Claims
- 16
Classified under
H10B 12/315 Electricity & electronicsH10B 12/0335 Electricity & electronicsH10B 12/34 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.