Samsung patents memory chip test that ignores minor defects
Samsung has been granted a patent for a memory device that uses a built-in self-test circuit to check for faulty storage cells. The system tests multiple memory sections in parallel and identifies if a failure is a single bad cell or two bad cells next to each other. If the damage fits these specific patterns, the chip marks the section as usable rather than discarding the entire bank.
In the filing’s own words
A memory device comprising a memory core including a memory cell array including a plurality of memory cells, the memory cell array being divided into a plurality of memory banks, a Built-In Self Test (BIST) circuit configured to select a target memory bank from the plurality of memory banks and perform a parallel test on the target memory bank, and a control circuit configured to control the parallel test. The BIST circuit may determine at least one defective memory cell outputting a defective bit among target memory cells included in the target memory bank, and may determine whether the defective memory cell is a single defective memory cell or an adjacent double defective memory cell, and the control circuit May determine the target memory bank to be a defective memory bank when the defective memory cell is not the single defective memory cell and the adjacent double defective memory cell.
What exactly they claim (claim 1)
1. A memory device comprising: a memory core including a memory cell array including a plurality of memory cells, the memory cell array arranged into a plurality of memory banks; a Built-In Self Test (BIST) circuit configured to select a target memory bank from the plurality of memory banks and perform a parallel test on the target memory bank among the plurality of memory banks; and a control circuit configured to control the parallel test, wherein the BIST circuit is configured to determine, in response to a one or more defective memory cells in the target memory bank outputting a defective bit among a plurality of target memory cells in the target memory bank, whether the defective memory cell is a single defective memory cell or an adjacent double defective memory cell, and wherein the control circuit is configured to determine the target memory bank to be a non-defective memory bank when the defective memory cell is the single defective memory cell or the adjacent double defective memory cell.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- Memory device and test method for the memory device
- Patent number
- US12763162B2
- Application number
- 18888271
- Filed
- Sep 18, 2024
- Granted
- Oct 13, 2026
- Inventors
- 4
- Claims
- 20
Classified under
G11C 29/44 Physics & computingMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.