Samsung patents memory chip design that manages signal noise internally
Samsung has been granted a patent for a nonvolatile memory system that includes a built-in circuit to manage electrical signals on the data lines. The design uses a specific chip to activate or deactivate signal dampening, known as on-die termination, depending on whether the memory is reading or writing data.
In the filing’s own words
A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.
What exactly they claim (claim 1)
1. A memory system comprising: a nonvolatile memory (NVM) including a first NVM chip and a second NVM chip; and a controller configured to control the NVM, wherein the controller comprises: a data pin configured to receive read data through a data bus during a read operation; a data strobe pin configured to receive a data strobe signal through a data strobe signal bus during the read operation; a read enable pin configured to transmit a read enable signal through a read enable signal bus during the read operation, the read enable signal comprising a preamble section, a toggling section and a postamble section; and an on-die termination (ODT) pin configured to transmit an ODT signal during the read operation, wherein the ODT signal enables and disables termination on at least one of the data bus, the data strobe signal bus, or the read enable signal bus, wherein the termination is enabled during the preamble section of the read enable signal after the read enable signal falling, and the termination is disabled during the postamble section of the read enable signal, wherein the first NVM chip includes a first ODT circuit, and the first ODT circuit is used to perform an ODT when the read data is read from the second NVM chip and the ODT signal is enabled.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- Nonvolatile memory including on-die-termination circuit and storage device including the nonvolatile memory
- Patent number
- US12763161B2
- Application number
- 18776432
- Filed
- Jul 18, 2024
- Granted
- Oct 13, 2026
- Inventors
- 5
- Claims
- 20
Classified under
G11C 29/025 Physics & computingG11C 5/063 Physics & computingG11C 7/1048 Physics & computingG11C 7/1057 Physics & computingG11C 7/1084 Physics & computingG11C 16/06 Physics & computingMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.