Samsung patents memory chip that fixes timing errors during reads and writes
This patent describes a memory device that adjusts the timing of its internal clock signals to ensure data is read and written accurately. It uses two separate circuits to correct timing for reading and writing at the same time, rather than doing them one after another.
In the filing’s own words
Provided is a memory device including a first pad configured to receive a read enable signal from a memory controller, a second pad configured to receive a read duty cycle correct command signal from the memory controller, a first duty correction circuit configured to perform a read duty cycle correct operation, based on the read duty cycle correct command signal received from the memory controller, when the read enable signal is received, and output a data strobe signal generated based on the read duty cycle correct operation, and a second duty correction circuit configured to receive the data strobe signal from the first duty correction circuit, generate first to fourth clock signals having different phases from each other based on the data strobe signal, and perform a write duty cycle correct operation to correct a duty cycle for the first clock signal and the third clock signal which have a phase difference of 180° and to correct a duty cycle for the second clock signal and the fourth clock signal which have a phase difference of 180°, wherein the read duty cycle correct operation and the write duty cycle correct operation are performed simultaneously.
What exactly they claim (claim 1)
1. A memory device comprising: a first pad configured to receive a read enable signal from a memory controller; a second pad configured to receive a read duty cycle correct command signal from the memory controller; a first duty correction circuit configured to perform a read duty cycle correct operation, based on the read duty cycle correct command signal received from the memory controller, when the read enable signal is received, and output a data strobe signal generated based on the read duty cycle correct operation; and a second duty correction circuit configured to receive the data strobe signal from the first duty correction circuit, generate first to fourth clock signals having different phases from each other based on the data strobe signal, and perform a write duty cycle correct operation to correct a duty cycle for the first clock signal and the third clock signal which have a phase difference of 180° and to correct a duty cycle for the second clock signal and the fourth clock signal which have a phase difference of 180°, wherein the read duty cycle correct operation and the write duty cycle correct operation are performed simultaneously.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- Memory device, memory system, and operating method of memory device
- Patent number
- US12763154B2
- Application number
- 18932736
- Filed
- Oct 31, 2024
- Granted
- Oct 13, 2026
- Inventors
- 4
- Claims
- 20
Classified under
G11C 16/32 Physics & computingG11C 16/0483 Physics & computingG11C 29/023 Physics & computingMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.