Samsung patents memory design that stabilizes dummy lines
This patent describes a layout for computer memory chips that includes extra, unused lines called dummy bitlines in the center of the memory area. It connects these dummy lines to the chip's control circuitry through a specific layer to apply a steady voltage, or bias, to them.
In the filing’s own words
A memory device includes first global bitlines adjacent to a first edge portion of a memory cell region, second global bitlines adjacent to a second edge portion of the memory cell region; dummy global bitlines in a central portion of the memory cell region, and a bitline sense amplifier in a sense amplifier region and connected to the first global bitlines, the second global bitlines, and the dummy global bitlines A first layer of the memory cell region is connected to a second layer of the sense amplifier region and is configured to apply a bias voltage to each of the dummy global bitlines.
What exactly they claim (claim 1)
1. A memory device comprising: first global bitlines adjacent to a first edge portion of a memory cell region; second global bitlines adjacent to a second edge portion of the memory cell region; dummy global bitlines in a central portion of the memory cell region; and a bitline sense amplifier in a sense amplifier region and connected to the first global bitlines, the second global bitlines, and the dummy global bitlines, wherein a first layer of the memory cell region is connected to a second layer of the sense amplifier region, said connection being through a line different from a global bitline of the memory cell region, wherein the second layer of the sense amplifier region is connected to at least one dummy global bitline, and wherein by said connection of the first layer of the memory cell region to the second layer of the sense amplifier region, the first layer is configured to apply a bias voltage to the at least one dummy global bitline.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- Memory device for biasing dummy global bitline
- Patent number
- US12763134B2
- Application number
- 18538260
- Filed
- Dec 13, 2023
- Granted
- Oct 13, 2026
- Inventors
- 8
- Claims
- 10
Classified under
G11C 11/4094 Physics & computingG11C 11/4091 Physics & computingG11C 11/4099 Physics & computingMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.