Samsung patents stacked memory design to save space in chips

1. A non-volatile memory device comprising: a first semiconductor layer comprising a first cell region in which a first memory cell array is disposed, a second cell region in which a second memory cell array is disposed, and a first metal pad layer, wherein the first memory cell array and the second memory cell array each comprise a plurality of word lines stacked in a vertical direction, a plurality of memory cells respectively connected to the plurality of word lines, and a plurality of bit lines; and a second semiconductor layer comprising a page buffer circuit region in which a page buffer circuit connected to the first memory cell array and the second memory cell array is disposed, and a second metal pad layer, wherein the second semiconductor layer is connected to the first semiconductor layer in the vertical direction through bonding by the first metal pad layer and the second metal pad layer, wherein the page buffer circuit includes at least one transistor that overlaps a boundary region within the first semiconductor layer between the first cell region and the second cell region when viewed from the vertical direction, wherein the page buffer circuit comprises, within the second semiconductor layer: a first switch connected between a page buffer and a first bit line connected to the first memory cell array; a second switch connected between the page buffer and a second bit line connected to the second memory cell array; and the page buffer comprising a sensing latch connected to the first switch and the second switch in common, and wherein at least one of the first switch, the second switch, and the page buffer overlaps the boundary region when viewed from the vertical direction.