Samsung patents stacked memory design with split connection zones

1. A semiconductor device, comprising: a first structure having a first side surface and a second side surface opposing each other, and including a first memory block and a second memory block sequentially arranged in a first direction from the first side surface to the second side surface; and a second structure including a peripheral circuit and overlapping the first structure, wherein the first memory block has a first connection region, a first memory cell array region, and a second connection region sequentially arranged in the first direction, wherein the second memory block has a third connection region, a second memory cell array region, and a fourth connection region sequentially arranged in the first direction, wherein the first memory block includes first gate electrodes that are spaced apart from each other and extend from the first connection region to the second connection region passing through the first memory cell array region, wherein the second memory block includes second gate electrodes that are spaced apart from each other and extend from the third connection region to the fourth connection region passing through the second memory cell array region, wherein the first gate electrodes of the first memory block include: first word lines having first word line pads that are disposed in the second connection region; and a first upper gate line having a first upper gate pad that is disposed in the first connection region and disposed on the first word lines, wherein the second gate electrodes of the second memory block include: second word lines having second word line pads that are disposed in the third connection region; and a second upper gate line having a second upper gate pad that is disposed in the fourth connection region and disposed on the second word lines, and wherein the first structure includes: first word line contact plugs connected to the first word line pads; a first upper gate contact plug connected to the first upper gate pad; second word line contact plugs connected to the second word line pads; and a second upper gate contact plug connected to the second upper gate pad.