Samsung patents chip packaging design with specific wiring layers
This patent describes a method for packaging semiconductor chips using a redistribution layer on a wafer-level chip scale package. It details how insulating layers, wiring, and protective coatings are arranged to connect the chip's internal pads to external conductive bumps.
In the filing’s own words
A semiconductor package includes: a semiconductor chip having chip pads disposed on a first surface thereof; a redistribution wiring layer formed on the first surface, wherein the redistribution wiring layer includes an insulating layer, redistribution wirings, a protective layer, and an under bump metallurgy (UBM) pad of UBM pads, wherein the insulating layer is formed on the first surface, wherein the redistribution wirings are provided on the insulating layer and are electrically connected to the chip pads, wherein the protective layer is provided on the insulating layer and has an opening that exposes at least a portion of a first redistribution wiring of the redistribution wirings, and wherein the under bump metallurgy (UBM) pad is provided on the at least a portion of the first redistribution wiring that is exposed by the opening; and conductive bumps disposed on the UBM pads of the redistribution wiring layer.
What exactly they claim (claim 1)
1. A semiconductor package, comprising: a semiconductor chip having chip pads disposed on a first surface thereof; a redistribution wiring layer formed on the first surface of the semiconductor chip, wherein the redistribution wiring layer includes at least one insulating layer, redistribution wirings, a protective layer, and an under bump metallurgy (UBM) pad of UBM pads, wherein the at least one insulating layer is formed on the first surface of the semiconductor chip, wherein the redistribution wirings are provided on the at least one insulating layer and are electrically connected to the chip pads, wherein the protective layer is provided on the at least one insulating layer and has an opening that exposes at least a portion of a first redistribution wiring of the redistribution wirings, and wherein the under bump metallurgy (UBM) pad is provided on the at least a portion of the first redistribution wiring that is exposed by the opening of the protective layer and spaced apart from an inner wall of the opening of the protective layer; and conductive bumps disposed on the UBM pads of the redistribution wiring layer, wherein the conductive bumps contact a portion of the redistribution wiring that is exposed by the opening of the protective layer.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- Semiconductor package comprising redistribution layer on wafer level chip scale package (WLCSP)
- Patent number
- US12757805B2
- Application number
- 18459821
- Filed
- Sep 1, 2023
- Granted
- Oct 6, 2026
- Inventors
- 1
- Claims
- 20
Classified under
H10W 90/701 Electricity & electronicsH10W 70/65 Electricity & electronicsH10W 70/66 Electricity & electronicsH10W 70/685 Electricity & electronicsH10W 74/137 Electricity & electronicsH10W 70/05 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.