Samsung patents chip design with metal edges to improve connection
Samsung has been granted a patent for a semiconductor package that connects two chips using a specific bonding structure. The design features a metal pad with a conductive barrier layer that extends horizontally over the top edge of the metal. This shape helps seal the connection between the two chips with an insulating layer.
In the filing’s own words
A semiconductor package includes a first semiconductor chip including a first semiconductor device, a second semiconductor chip including a second semiconductor device, and a bonding structure between the first and second semiconductor chips, the bonding structure including a first bonding pad, a first bonding insulating layer, a second bonding pad in contact with the first bonding pad, and a second bonding insulating layer in contact with the first bonding insulating layer. The first bonding pad may include a first pad metal layer and a first conductive barrier layer surrounding the first pad metal layer, and the first conductive barrier layer may include a horizontal extension portion extending on an edge of an upper surface of the first pad metal layer.
What exactly they claim (claim 1)
1. A semiconductor package comprising: a first semiconductor chip comprising a first semiconductor device; a second semiconductor chip comprising a second semiconductor device; and a bonding structure between the first semiconductor chip and the second semiconductor chip, the bonding structure comprising: a first bonding pad electrically connected to the first semiconductor device; a first bonding insulating layer surrounding a sidewall of the first bonding pad; a second bonding pad electrically connected to the second semiconductor device and in contact with the first bonding pad; and a second bonding insulating layer surrounding a sidewall of the second bonding pad and in contact with the first bonding insulating layer, wherein the first bonding pad comprises: a first pad metal layer in a first pad opening portion of the first bonding insulating layer; and a first conductive barrier layer having a first portion surrounding a sidewall and a bottom surface of the first pad metal layer and disposed between the first bonding insulating layer and the first pad metal layer, and wherein the first conductive barrier layer comprises a horizontal extension portion, having a same material as the first portion, extending on an edge of an upper surface of the first pad metal layer.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- Semiconductor package and method of manufacturing the same
- Patent number
- US12757790B2
- Application number
- 18364802
- Filed
- Aug 3, 2023
- Granted
- Oct 6, 2026
- Inventors
- 6
- Claims
- 20
Classified under
H10W 90/00 Electricity & electronicsH10W 74/111 Electricity & electronicsH10W 72/019 Electricity & electronicsH10W 72/01951 Electricity & electronicsH10W 72/921 Electricity & electronicsH10W 72/923 Electricity & electronicsMore from Samsung in Chips & hardware
- Samsung patents chip that combines camera and screen Oct 13, 2026
- Samsung patents faster chip testing using machine learning Sep 1, 2026
- Samsung patents radar method to pinpoint target direction more accurately Sep 1, 2026
- Samsung patents memory chip that searches data by content, not address Sep 1, 2026
- Samsung patents chip design that skips empty data to speed up AI Sep 1, 2026
Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.