Samsung patents chip package with self-forming barrier layers
Samsung has been granted a patent for a semiconductor package design that uses a stacked structure of conductive layers and insulating materials to connect a chip. The design includes specific barrier layers that form naturally between the conductive and insulating parts to protect the connection points.
In the filing’s own words
A semiconductor package includes a first redistribution structure including a top surface, a chip arranged on the top surface of the first redistribution structure the chip having a top surface, bottom surface, and side surfaces, and a package body arranged on the top surface of the first redistribution structure to cover the side surfaces of the chip. The first redistribution structure includes a plurality of redistribution layers stacked in a vertical direction, a plurality of redistribution insulating layers stacked in the vertical direction and which insulate the plurality of redistribution layers from each other, a plurality of redistribution vias buried in a plurality of redistribution via holes penetrating the plurality of redistribution insulating layers and electrically connecting the plurality of redistribution layers to each other, and a plurality of self-formed barrier layers formed between side surfaces of the plurality of redistribution layers and the plurality of redistribution insulating layers.
What exactly they claim (claim 1)
1. A semiconductor package comprising: a first redistribution structure including a top surface; a chip arranged on the top surface of the first redistribution structure, the chip having a top surface, bottom surface, and side surfaces; and a package body arranged on the top surface of the first redistribution structure to cover the side surfaces of the chip, wherein the first redistribution structure comprises: a plurality of redistribution layers stacked in a vertical direction; a plurality of redistribution insulating layers stacked in the vertical direction and which insulate the plurality of redistribution layers from each other; a plurality of redistribution vias buried in a plurality of redistribution via holes penetrating the plurality of redistribution insulating layers and electrically connecting the plurality of redistribution layers to each other; and a plurality of self-formed barrier layers formed between side surfaces of the plurality of redistribution layers and the plurality of redistribution insulating layers.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- Semiconductor package
- Patent number
- US12757763B2
- Application number
- 18236090
- Filed
- Aug 21, 2023
- Granted
- Oct 6, 2026
- Inventors
- 4
- Claims
- 20
Classified under
H10W 70/65 Electricity & electronicsH10W 70/685 Electricity & electronicsH10W 70/69 Electricity & electronicsH10W 74/111 Electricity & electronicsH10W 90/00 Electricity & electronicsH10W 70/60 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.