Samsung patents 3D chip design with metal plates to isolate stacked gates
Samsung has secured a patent for a semiconductor device that stacks gate electrodes vertically on a second substrate placed above a first one. The design features a metal plate on top of the second substrate that connects to the channel layers and extends downward as a vertical conductive layer to isolate the stacked gates.
In the filing’s own words
A semiconductor device includes a first semiconductor structure including a lower bonding structure, and a second semiconductor structure including a second substrate disposed on the first semiconductor structure, gate electrodes stacked and spaced apart from each other in a first direction perpendicular to a lower surface of the second substrate, an upper bonding structure bonded to the lower bonding structure, a plate conductive layer disposed on an upper surface of the second substrate, electrically connected to a channel layer, and including a metal material, and an isolation structure penetrating an entirety of the gate electrodes and extending in a second direction perpendicular to the first direction. The isolation structure includes a vertical conductive layer that extends from and is integrated with the plate conductive layer, and that includes a same metal material as the metal material of the plate conductive layer.
What exactly they claim (claim 1)
1. A semiconductor device comprising: a first semiconductor structure including a first substrate, circuit devices disposed on the first substrate, a lower wiring structure electrically connected to the circuit devices, and a lower bonding structure connected to the lower wiring structure; and a second semiconductor structure including: a second substrate disposed on the first semiconductor structure, gate electrodes stacked and spaced apart from each other in a vertical direction perpendicular to a lower surface of the second substrate, channel structures that penetrate the gate electrodes, that extend in the vertical direction, and that each include a channel layer, an upper wiring structure disposed below the gate electrodes and below the channel structures, an upper bonding structure connected to the upper wiring structure and bonded to the lower bonding structure, a plate conductive layer disposed on an upper surface of the second substrate, that is electrically connected to the channel layer, and that includes a metal material, and an isolation structure that extends in the vertical direction, that penetrates an entirety of the gate electrodes, and that has a width in a horizontal direction perpendicular to the vertical direction, wherein the isolation structure includes a vertical conductive layer that extends from the plate conductive layer, that is integrated with the plate conductive layer, and that includes a same metal material as the metal material of the plate conductive layer.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- Semiconductor device and electronic system including the same
- Patent number
- US12757720B2
- Application number
- 18080402
- Filed
- Dec 13, 2022
- Granted
- Oct 6, 2026
- Inventors
- 3
- Claims
- 13
Classified under
H10W 20/435 Electricity & electronicsH10B 41/35 Electricity & electronicsH10B 41/41 Electricity & electronicsH10B 43/35 Electricity & electronicsH10B 43/40 Electricity & electronicsH10D 30/6892 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.