Samsung patents 3D memory design with tapered connections

1. A semiconductor device comprising: a first substrate structure including a first substrate, circuit elements at least partially disposed on or in the first substrate, and first bonding metal layers disposed on the circuit elements; and a second substrate structure disposed on the first substrate structure, wherein the second substrate structure is connected to the first substrate structure, wherein the second substrate structure includes: a plate layer including a conductive material, the plate layer having first and second faces opposite to each other; gate electrode layers disposed on the first face of the plate layer, the gate electrode layers are stacked on top of each other in a first direction perpendicular to the first face of the plate layer and are spaced apart from each other in the first direction; channel structures extending through the gate electrode layers in the first direction; word-line cutting structures extending through the gate electrode layers, the word-line cutting structures extend in each of the first direction and a second direction intersecting the first direction wherein the word-line cutting structures are spaced apart from each other along a third direction intersecting each of the first and second directions and parallel to the first face of the plate layer, via structures disposed on the second face of the plate layer, the via structures extending in the third direction, wherein the via structures are spaced apart from each other along the second direction, each of the via structures includes a bottom face facing the second face of the plate layer and a top face opposite the bottom face; via connecting structures disposed on the top face of the via structures, the via connecting structures extending in the second direction, wherein the via connecting structures are spaced apart from each other along the third direction, each of the via connecting structures includes a bottom face facing the top face of the via structures and a top face opposite the bottom face; and second bonding metal layers disposed under the channel structures and the gate electrode layers and connected to the first bonding metal layers, wherein a width of the bottom face of each of the via structures is greater than a width of the top face of each of the via structures, wherein a width of the bottom face of each of the via connecting structures is less than a width of the top face of each of the via connecting structures, wherein in a plan view of the semiconductor device, the second substrate structure includes a first area including the channel structures, and second and third areas sequentially arranged outwardly from the first area, wherein the second substrate structure includes: cell contact structures disposed in the second area, each of the cell contact structures are electrically connected to one of the gate electrode layers; dummy channel structures disposed in the second area, the dummy channel structures are electrically isolated from the gate electrode layers; source contact structures disposed in the second area, the source contact structures do not extend through the gate electrode layers and extending through at least a portion of the plate layer; and through structures disposed in the third area, the through structures are not disposed on the plate layer, wherein the through structures are electrically connected to the circuit elements, wherein each of the via structures includes: a first extension disposed in the first and second areas and extending in the third direction; and a first spaced portion disposed in the third area and spaced apart from the first extension, wherein the first spaced portion is connected to one of the through structures.