Samsung patents stacked camera sensor design to reduce noise
Samsung describes a three-layer camera sensor that stacks image pixels, control circuits, and processing chips vertically. The design uses a specific trapezoidal shape for the vertical connections between layers to keep them aligned and reduce electrical interference.
In the filing’s own words
The inventive concepts provide a three-layered stacked image sensor in which misalignment between a through electrode and a pad is reduced and coupling noise between adjacent pads is reduced, and methods of manufacturing the same. The three-layered stacked image sensor includes an upper chip including pixels arranged in a two-dimensional array structure and a first wiring layer, each of pixels including a photodiode, a transfer gate, and a floating diffusion region, an intermediate chip including a source follower gate, a select gate, and a reset gate corresponding to each of pixels, a first silicon layer, and a second wiring layer, and a lower chip including an image sensor processor, a third wiring layer, and a second silicon layer, a cross-section of an upper portion of a through electrode extending from the second wiring layer through the first silicon layer having an inverted trapezoidal structure.
What exactly they claim (claim 1)
1. A three-layered stacked image sensor comprising: an upper chip comprising a plurality of pixels arranged in a two-dimensional array structure, and a first wiring layer beneath the plurality of pixels, each of the plurality of pixels comprising a photodiode, a transfer gate, and a floating diffusion region; an intermediate chip comprising a source follower gate, a select gate, and a reset gate corresponding to each of the plurality of pixels, a first silicon layer at an upper portion of the intermediate chip, and a second wiring layer at a lower portion of the intermediate chip; and a lower chip comprising an image sensor processor, a third wiring layer at an upper portion of the lower chip, and a second silicon layer at a lower portion of the lower chip, the upper chip, the intermediate chip, and the lower chip sequentially stacked from a top, a first pad of the first wiring layer and an upper pad of the intermediate chip bonded to each other, a second pad of the second wiring layer and a third pad of the third wiring layer bonded to each other, the upper pad on a through electrode extending from the second wiring layer through the first silicon layer, and a cross-section of an upper portion of the through electrode having an inverted trapezoidal structure.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- Three-layered stacked image sensor and method of manufacturing the same
- Patent number
- US12757514B2
- Application number
- 18354040
- Filed
- Jul 18, 2023
- Granted
- Oct 6, 2026
- Inventors
- 5
- Claims
- 17
Classified under
H10F 39/811 Electricity & electronicsH10F 39/026 Electricity & electronicsH10F 39/8027 Electricity & electronicsH10F 39/8053 Electricity & electronicsH10F 39/8063 Electricity & electronicsH10F 39/807 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.