Samsung patents stacked chip design with internal insulation layers
Samsung has been granted a patent for a semiconductor device that stacks two transistor layers vertically to save space. The design uses a middle isolation structure made of stacked semiconductor layers to separate the top and bottom components. This setup includes specific conductive parts that are electrically disconnected from the main gates to manage the device's internal structure.
In the filing’s own words
Provided is a semiconductor device which includes: a 1 st source/drain region connected to a 1 st channel structure which is controlled by a 1 st gate structure; a 2 nd source/drain region, above the 1 st source/drain region, connected to a 2 nd channel structure which is controlled by a 2 nd gate structure; and a middle isolation structure between the 1 st gate structure and the 2 nd gate structure, wherein the middle isolation structure comprises two or more vertically-stacked semiconductor layers.
What exactly they claim (claim 1)
1. A semiconductor device comprising: a 1 st source/drain region connected to a 1 st channel structure which is controlled by a 1 st gate structure; a 2 nd source/drain region, above the 1 st source/drain region, connected to a 2nd channel structure which is controlled by a 2 nd gate structure; and a middle isolation structure between the 1 st gate structure and the 2 nd gate structure, wherein the middle isolation structure comprises two or more semiconductor layers which are vertically stacked, wherein at least one of a portion of the 1 st gate structure and a portion of the 2 nd gate structure is disposed between the two or more semiconductor layers, and wherein the at least one of the portion of the 1 st gate structure and the portion of the 2 nd gate structure comprises a conductive material that is not electrically connected to a remaining portion of the 1 st gate structure or a remaining portion of the 2 nd gate structure.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- 3D-stacked semiconductor device including middle isolation structure and BSPDN structure
- Patent number
- US12757485B2
- Application number
- 18521323
- Filed
- Nov 28, 2023
- Granted
- Oct 6, 2026
- Inventors
- 3
- Claims
- 20
Classified under
H10D 84/856 Electricity & electronicsH10D 30/014 Electricity & electronicsH10D 30/43 Electricity & electronicsH10D 30/6729 Electricity & electronicsH10D 30/6735 Electricity & electronicsH10D 62/121 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.