Samsung patents chip design with different contact heights for transistors
This patent describes a method for building integrated circuits where the metal connections to two different types of transistors have different lengths. One connection is shorter and stops higher up, while the other is longer and extends further down past the transistor's channel region.
In the filing’s own words
An integrated circuit device includes a first transistor comprising a first conductivity type, which includes a first channel region and a first source/drain region, a second transistor comprising a second conductivity type, which includes a second channel region and a second source/drain region, a first contact structure that contacts the first source/drain region and comprising a first length, and the first contact structure extends from above the first source/drain region and beyond an uppermost surface of the first channel region by a first vertical distance, and a second contact structure that contacts the second source/drain region and having a second length that is greater than the first length, the second contact extends from above the second source/drain region and beyond an uppermost surface of the second channel region by a second vertical distance, which is greater than the first vertical distance.
What exactly they claim (claim 1)
1. An integrated circuit device comprising: a first transistor comprising a first conductivity type, the first transistor comprising a first fin-type active region on a first area of a substrate, a first channel region on the first fin-type active region, and a first source/drain region that is on the first fin-type active region and contacts the first channel region; a second transistor comprising a second conductivity type, the second transistor comprising a second fin-type active region on a second area of the substrate, a second channel region on the second fin-type active region, and a second source/drain region on the second fin-type active region and that contacts the second channel region; a first contact structure that contacts the first source/drain region and comprises a first length in a vertical direction, wherein the first contact structure extends from above the first source/drain region and beyond an uppermost surface of the first channel region by a first vertical distance; a second contact structure that contacts the second source/drain region and comprises a second length in the vertical direction, wherein the second contact structure extends from above the second source/drain region and beyond an uppermost surface of the second channel region by a second vertical distance; and a semiconductor capping layer that contacts an upper surface of the second source/drain region, wherein a density of the semiconductor capping layer is less than a density of the second source/drain region, wherein the second vertical distance is greater than the first vertical distance, and wherein the second length of the second contact structure is greater than the first length of the first contact structure.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- Integrated circuit device
- Patent number
- US12757482B2
- Application number
- 18476688
- Filed
- Sep 28, 2023
- Granted
- Oct 6, 2026
- Inventors
- 7
- Claims
- 20
Classified under
H10D 84/85 Electricity & electronicsH10D 84/017 Electricity & electronicsH10D 84/0186 Electricity & electronicsH10D 84/038 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.