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Samsung patents vertical transistor design using silicide buffer layer

Patent drawing
Patent drawing from the official filing.

Samsung has been granted a patent for a semiconductor device structure that stacks components vertically on a chip. The design places a silicide material buffer between a metal oxide layer and an oxide channel to improve the connection between the transistor's parts.

Why it mattersThis filing details a specific method for building transistors, which could lead to more efficient or compact computer chips in the future.

In the filing’s own words

Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device includes a lower electrode on a substrate, a metal oxide on the lower electrode, a buffer on the metal oxide, an oxide channel in the buffer, a gate insulating layer in the oxide channel, a gate electrode in the gate insulating layer, and an upper electrode on the gate electrode, and the buffer may include a silicide material.

What exactly they claim (claim 1)

1. A semiconductor device comprising: a substrate; a lower electrode on the substrate; a metal oxide on the lower electrode; a first buffer on the metal oxide; an oxide channel on the first buffer; a gate insulating layer contacting the oxide channel; a gate electrode contacting the gate insulating layer; and an upper electrode on the oxide channel, wherein the first buffer is between the metal oxide and the oxide channel, the first buffer includes a silicide material, the upper electrode and the lower electrode are spaced apart from each other in a perpendicular direction that is perpendicular to the substrate, and a longitudinal direction of the oxide channel is perpendicular to the substrate.

Facts

Company
Samsung (Samsung Electronics Co., Ltd.)
Official title
Semiconductor device and method of manufacturing the same
Patent number
US12757472B2
Application number
18481444
Filed
Oct 5, 2023
Granted
Oct 6, 2026
Inventors
5
Claims
15

Classified under

H10D 64/62 Electricity & electronicsH10D 30/6728 Electricity & electronicsH10D 30/6755 Electricity & electronicsH10D 30/6757 Electricity & electronicsH10D 64/011 Electricity & electronicsH10D 99/00 Electricity & electronics

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.