Samsung patents 3D chip layout with stacked channel sheets
This patent describes a semiconductor structure where channel layers are stacked vertically as separate sheets between insulating walls. Gates and source/drain contacts are arranged around these stacked sheets to create a complex three-dimensional transistor design.
In the filing’s own words
A semiconductor device includes a first and second channel separation structures extending in a first direction and spaced apart from each other in a second direction, first gate structures spaced apart from each other in the first direction between the first and second channel separation structures and in contact with the first and second channel separation structures, first and second channel patterns including first and second sheet patterns, respectively, spaced apart from each other in a third direction and in contact with the corresponding first and second channel separation structures, first and second source/drain patterns between the first and second channel separation structures, the first source/drain patterns in contact with the first channel patterns and the first channel separation structure, the second source/drain patterns in contact with the second channel patterns and the second channel separation structure, and first gate separation structures between the first and second source/drain patterns.
What exactly they claim (claim 1)
1. A semiconductor device, comprising: a first channel separation structure extending in a first direction; a second channel separation structure spaced apart from the first channel separation structure in a second direction intersecting the first direction and extending in the first direction; a plurality of first gate structures spaced apart from each other in the first direction between the first and second channel separation structures, the first gate structures being respectively in contact with the first and second channel separation structures and including respective first gate electrodes and respective first gate insulating films; first channel patterns including a respective plurality of first sheet patterns, which are spaced apart from each other in a third direction, perpendicular to the first and second directions, and are in contact with the first channel separation structure; second channel patterns including a respective plurality of second sheet patterns, which are spaced apart from each other in the third direction and are in contact with the second channel separation structure; first source/drain patterns between the first and second channel separation structures and respective in contact with the first channel patterns and the first channel separation structure; second source/drain patterns between the first and second channel separation structures and respectively in contact with the second channel patterns and the second channel separation structure; and first gate separation structures between the first source/drain patterns and the second source/drain patterns.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- Semiconductor device and method of fabricating the same
- Patent number
- US12757459B2
- Application number
- 18411313
- Filed
- Jan 12, 2024
- Granted
- Oct 6, 2026
- Inventors
- 6
- Claims
- 20
Classified under
H10D 62/235 Electricity & electronicsH10D 64/258 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.