Samsung patents chip design mixing two types of electrical connections
Samsung has secured a patent for a semiconductor structure where the source and drain areas of a transistor use layers with different electrical properties. The design stacks a lower layer with one conductivity type and an upper layer with a different type to create a specific contact point.
In the filing’s own words
A semiconductor device includes: an active pattern which includes a first lower pattern and first sheet patterns, wherein the first lower pattern extends in a first direction, and the plurality of first sheet patterns are spaced apart from the first lower pattern in a second direction crossing the first direction; a gate structure, which includes a gate electrode and a gate spacer extending in a third direction intersecting the first and second directions, disposed on the active pattern; a first source/drain pattern adjacent to a side of the gate structure; and a second source/drain pattern which is spaced apart from the first source/drain pattern with the gate structure interposed therebetween, wherein the first source/drain pattern includes: a lower layer including a first conductivity type and disposed on the first lower pattern, and an upper layer including a second conductivity type, wherein the second source/drain pattern has the second conductivity type.
What exactly they claim (claim 1)
1. A semiconductor device comprising: an active pattern which includes a first lower pattern and a plurality of first sheet patterns, wherein the first lower pattern extends in a first direction, and the plurality of first sheet patterns are spaced apart from the first lower pattern in a second direction crossing the first direction; a gate structure, which includes a gate electrode and a gate spacer extending in a third direction intersecting the first direction and the second direction, disposed on the active pattern; a first source/drain pattern disposed adjacent to a first side of the gate structure; and a second source/drain pattern which is spaced apart from the first source/drain pattern with the gate structure interposed therebetween, wherein the first source/drain pattern includes: a lower layer including a first conductivity type and disposed on the first lower pattern, and an upper layer including a second conductivity type, which is different from the first conductivity type, and disposed on the lower layer, and a capping film including the first conductivity type and disposed on the upper layer, wherein the second source/drain pattern has the second conductivity type.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- Semiconductor device having source/drain pattern including multiple layers with different conductivity type
- Patent number
- US12757458B2
- Application number
- 18534824
- Filed
- Dec 11, 2023
- Granted
- Oct 6, 2026
- Inventors
- 1
- Claims
- 18
Classified under
H10D 62/151 Electricity & electronicsH10D 30/014 Electricity & electronicsH10D 30/43 Electricity & electronicsH10D 30/6729 Electricity & electronicsH10D 30/6735 Electricity & electronicsH10D 62/121 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.