Samsung patents 3D chip design with differently sized stacked transistors
Samsung has been granted a patent for a semiconductor device where transistors are stacked vertically in layers. The design allows the upper and lower layers of these transistors to have different physical thicknesses and dimensions, rather than being identical copies.
In the filing’s own words
Provided is a multi-stack semiconductor device including: a substrate; a lower-stack nanosheet transistor including two or more lower channel layers surrounded by a lower gate structure, the lower channel layers connecting lower source/drain regions; and an upper-stack nanosheet transistor formed above the lower-stack nanosheet transistor, and including two or more upper channel layers surrounded by an upper gate structure, the upper channel layers connecting upper source/drain regions, wherein the lower-stack nanosheet transistor and the upper-stack nanosheet transistor have at least one of: a difference between a thickness of one of the lower channel layers and a thickness of one of the upper channel layers; and a difference between a thickness of the lower gate structure between two adjacent lower channel layers and a thickness of the upper gate structure between two adjacent upper channel layers.
What exactly they claim (claim 1)
1. A multi-stack semiconductor device comprising: a substrate; a lower-stack nanosheet transistor comprising at least one lower channel layer surrounded by a lower gate structure, the at least one lower channel layer connecting lower source/drain regions; and an upper-stack nanosheet transistor formed above the lower-stack nanosheet transistor, and comprising at least one upper channel layer surrounded by an upper gate structure, the at least one upper channel layer connecting upper source/drain regions, wherein one of the at least one lower channel layer and one of the at least one upper channel layer have different thicknesses, and wherein a thickness of the lower-stack nanosheet transistor is different from a thickness of the upper-stack nanosheet transistor.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- 3D-stacked semiconductor device having different channel and gate dimensions across lower stack and upper stack
- Patent number
- US12757455B2
- Application number
- 17945695
- Filed
- Sep 15, 2022
- Granted
- Oct 6, 2026
- Inventors
- 4
- Claims
- 23
Classified under
H10D 62/121 Electricity & electronicsH10D 30/6757 Electricity & electronicsH10D 62/151 Electricity & electronicsH10D 84/0142 Electricity & electronicsH10D 84/0179 Electricity & electronicsH10D 84/8311 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.