Samsung patents 3D memory chip with mixed-type source layer
Samsung has been granted a patent for a semiconductor device where the memory cells are stacked vertically on top of the control circuits. The design features a shared source layer at the top of the vertical channel that contains two different types of electrical impurities to manage how current flows.
In the filing’s own words
A semiconductor device includes a peripheral circuit structure and a cell structure stacked on the peripheral circuit structure. The cell structure includes a plurality of gate electrodes spaced apart from each other in a vertical direction, a channel structure passing through the plurality of gate electrodes and extending in the vertical direction, the channel structure having a first end close to the peripheral circuit structure and a second end opposite to the first end, and a common source layer covering the second end of the channel structure. The channel structure includes a channel layer extending in the vertical direction, the common source layer includes a first region and a second region that contain impurities of different conductivity types, and the first region of the common source layer is connected to at least a portion of the channel layer.
What exactly they claim (claim 1)
1. A semiconductor device comprising: a peripheral circuit structure; and a cell structure stacked on the peripheral circuit structure, the cell structure comprising a cell region, a connection region located next to the cell region in a first horizontal direction, and a peripheral circuit connection region surrounding the cell region and the connection region, wherein the cell structure comprises: a plurality of gate electrodes, each of the gate electrodes being arranged in the cell region and spaced apart from each other in a vertical direction; a channel structure passing through the gate electrodes in the cell region and extending in the vertical direction, the channel structure having a first end close to the peripheral circuit structure and a second end opposite to the first end; and a common source layer disposed above the plurality of gate electrodes and covering the second end of the channel structure, wherein the channel structure comprises a channel layer extending in the vertical direction, wherein the common source layer comprises a first region and a second region that contain impurities of different conductivity types, and wherein the first region of the common source layer is connected to at least a portion of the channel layer.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- Semiconductor device
- Patent number
- US12757434B2
- Application number
- 18629093
- Filed
- Apr 8, 2024
- Granted
- Oct 6, 2026
- Inventors
- 7
- Claims
- 20
Classified under
H10D 30/63 Electricity & electronicsH10B 80/00 Electricity & electronicsH10D 62/149 Electricity & electronicsH10D 62/292 Electricity & electronicsH10W 90/00 Electricity & electronicsH10W 90/792 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.