Samsung patents memory chip design with stacked wiring layers
Samsung has been granted a patent for a semiconductor memory device that uses two separate substrates to organize its internal components. The design places data storage and control circuits on different layers, connected by vertical wires that pass through the second substrate to link the parts together.
In the filing’s own words
A semiconductor memory device including an active pattern on a first substrate and comprising a first and second surfaces opposite to each other in a first direction, a data storage pattern between the active pattern and the first substrate and connected to a first surface of the active pattern, a bit line on the active pattern, connected to a second surface of the active pattern, and extending in a second direction, a word line on a sidewall of the active pattern, a second substrate, a peripheral gate structure on a first surface of the second substrate, a first connection wiring structure on the first surface of the second substrate and connected to the peripheral gate structure and bit line, a second connection wiring structure on a second surface of the second substrate and a through via penetrating the second substrate and connecting the first and second connection wiring structures.
What exactly they claim (claim 1)
1. A semiconductor memory device comprising: an active pattern disposed on a first substrate and comprising a first surface and a second surface opposite to each other in a first direction, and a first sidewall and a second sidewall opposite to each other in a second direction, the second direction intersecting the first direction; a data storage pattern disposed between the active pattern and the first substrate and connected to the first surface of the active pattern; a bit line disposed on the active pattern, connected to the second surface of the active pattern, and extending in the second direction; a word line disposed on the first sidewall of the active pattern and extending in a third direction, the third direction intersecting the first direction and the second direction; a second substrate comprising a first surface and a second surface opposite to each other in the first direction, the first surface of the second substrate facing the first substrate; a peripheral gate structure disposed on the first surface of the second substrate; a first connection wiring structure disposed on the first surface of the second substrate and connected to the peripheral gate structure and the bit line; a second connection wiring structure disposed on the second surface of the second substrate; and a through via penetrating the second substrate and connecting the first connection wiring structure and the second connection wiring structure.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- Semiconductor memory device
- Patent number
- US12757413B2
- Application number
- 18495519
- Filed
- Oct 26, 2023
- Granted
- Oct 6, 2026
- Inventors
- 6
- Claims
- 20
Classified under
H10B 80/00 Electricity & electronicsH10B 12/33 Electricity & electronicsH10B 12/482 Electricity & electronicsH10B 12/485 Electricity & electronicsH10B 12/488 Electricity & electronicsH10B 12/50 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.