Samsung patents chip layout that separates memory and logic areas
This patent describes a specific way to build a semiconductor chip by using different insulating materials for the memory section and the control section. The design features a cell insulating layer that extends over the peripheral area, with a separate peripheral insulating layer filling the gaps between these extensions.
In the filing’s own words
A semiconductor device includes a substrate including a cell region and a peripheral region, a wiring structure on the cell and peripheral regions, a lower insulating layer on the wiring structure on the cell and peripheral regions, data storage patterns on the lower insulating layer on the cell region, a cell insulating layer on the lower insulating layer on the cell region and covering the data storage patterns, including cell extending portions extending above the lower insulating layer on the peripheral region in a first direction, the cell extending portions spaced apart from each other in a second direction, and a peripheral insulating layer on the lower insulating layer on the peripheral region and including a material different from that of the cell insulating layer. The peripheral insulating layer extends between the cell extending portions and is in contact with a side surface of the cell insulating layer.
What exactly they claim (claim 1)
1. A semiconductor device comprising: a substrate defining a cell region and a peripheral region; a wiring structure disposed in the cell region and the peripheral region; a lower insulating layer disposed on the wiring structure on the cell region and extending above the wiring structure on the peripheral region; a plurality of data storage patterns disposed on the lower insulating layer on the cell region; a cell insulating layer disposed on the lower insulating layer on the cell region and covering the plurality of data storage patterns, the cell insulating layer including a plurality of cell extending portions, wherein the plurality of cell extending portions extend above the lower insulating layer on the peripheral region in a first direction that is parallel to an upper surface of the substrate, and wherein the plurality of cell extending portions are spaced apart from each other in a second direction that is parallel to the upper surface of the substrate and intersects the first direction; and a peripheral insulating layer disposed on the lower insulating layer on the peripheral region and including a material different from the cell insulating layer, wherein the peripheral insulating layer extends between the plurality of cell extending portions and contacts a side surface of the cell insulating layer.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- Semiconductor device
- Patent number
- US12757409B2
- Application number
- 18400741
- Filed
- Dec 29, 2023
- Granted
- Oct 6, 2026
- Inventors
- 1
- Claims
- 20
Classified under
H10B 61/00 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.