Samsung patents 3D chip design using ferroelectric layers for memory
Samsung describes a semiconductor structure where a ferroelectric material is sandwiched between a conductive line and a semiconductor layer within a stacked 3D architecture. The design uses alternating insulating layers and specific contact points to create a compact memory cell that extends vertically from the base substrate.
In the filing’s own words
A semiconductor device comprises a substrate that extends in first and second directions and includes a cell region and an extension region that extends from the cell region in the first direction, first and second insulating layers alternately stacked on the substrate in a third direction, a conductive line disposed on one sidewall of the second insulating layer in the second direction, a conductive pillar that extends in the third direction and penetrates through the first insulating layer, a semiconductor layer disposed on one sidewall of the conductive pillar and that extends in the third direction, and a ferroelectric layer disposed between the conductive line and the semiconductor layer and that extends in the third direction. The conductive line includes first and second conductive patterns spaced apart from each other in the second direction, and the second insulating layer is disposed between the first and second conductive patterns.
What exactly they claim (claim 1)
1. A semiconductor device, comprising: a substrate that extends in first and second directions that cross each other, wherein the substrate includes a cell region and an extension region that extends from the cell region in the first direction; first and second insulating layers alternately stacked on the substrate in a third direction that crosses the first and second directions; a conductive line disposed on one sidewall of the second insulating layer in the second direction; a conductive pillar that extends in the third direction and penetrates through the first insulating layer; a semiconductor layer disposed on one sidewall of the conductive pillar and that extends in the third direction; a first contact connected to the conductive line and that extends in the third direction on the conductive line; and a ferroelectric layer disposed between the conductive line and the semiconductor layer and that extends in the third direction, wherein the conductive line includes first and second conductive patterns spaced apart from each other in the second direction, and the second insulating layer is disposed between the first and second conductive patterns, wherein the conductive line in the extension region has first and second regions alternatively arranged in the first direction, wherein the first contact is connected to the first region, and wherein the second insulating layer is disposed in the second region, wherein the conductive line has a stepwise shape in the extension region, and wherein the first contact is not formed in the second region, and wherein the second insulating layer is not disposed in the first region.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- Semiconductor device and method of fabricating the same
- Patent number
- US12757405B2
- Application number
- 18351407
- Filed
- Jul 12, 2023
- Granted
- Oct 6, 2026
- Inventors
- 2
- Claims
- 16
Classified under
H10B 51/20 Electricity & electronicsH10B 51/10 Electricity & electronicsH10D 30/0415 Electricity & electronicsH10D 30/701 Electricity & electronicsH10W 20/435 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.