Samsung patents 3D memory layout that saves space
Samsung has been granted a patent for a specific layout of 3D memory chips. The design places two vertical memory stacks side-by-side and routes their connection pads in opposite L-shapes to fit more components into a smaller area.
In the filing’s own words
A semiconductor device includes first and second cell arrays. The first cell array includes a first gate electrode that extends in a vertical direction, a first channel pattern on a side surface of the first gate electrode, and a first bit line electrically connected to the first channel pattern. The second cell array includes a second gate electrode that extends in the vertical direction, a second channel pattern on a side surface of the second gate electrode, and a second bit line electrically connected to the second channel pattern. A first bit line pad is electrically connected to the first bit line and a second bit line pad is electrically connected to the second bit line. The first bit line pad is spaced apart from the second bit line pad with the first and second cell arrays therebetween.
What exactly they claim (claim 1)
1. A semiconductor device comprising: a first cell array and a second cell array on a substrate and adjacent to each other in a first direction parallel to an upper surface of the substrate; the first cell array comprising: a first gate electrode that extends in a second direction perpendicular to the upper surface of the substrate; first channel patterns on a side surface of the first gate electrode and spaced apart from each other in the second direction; and a first bit line electrically connected to a corresponding first channel pattern among the first channel patterns, and the second cell array comprising: a second gate electrode that extends in the second direction; second channel patterns on a side surface of the second gate electrode and spaced apart from each other in the second direction; and a second bit line electrically connected to a corresponding second channel pattern among the second channel patterns; a first bit line pad electrically connected to the first bit line; and a second bit line pad electrically connected to the second bit line, wherein the first bit line pad is offset from the second bit line pad in both the first direction and a third direction which is parallel to the upper surface of the substrate and intersects the first direction, with the first and second cell arrays therebetween, and wherein the first bit line pad and the first bit line form a first L-shape, the second bit line pad and the second bit line form a second L-shape, and the first L-shape and the second L-shape are symmetric about the first direction.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- Highly integrated semiconductor device
- Patent number
- US12757404B2
- Application number
- 18170136
- Filed
- Feb 16, 2023
- Granted
- Oct 6, 2026
- Inventors
- 5
- Claims
- 20
Classified under
H10B 51/20 Electricity & electronicsH01L 23/5283 Electricity & electronicsH10B 51/10 Electricity & electronicsH10D 30/701 Electricity & electronicsH10D 64/689 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.