Samsung patents 3D chip layout using dummy stacks to protect circuits
Samsung describes a semiconductor design where non-functional 'dummy' structures are stacked in the outer areas of a chip. These dummy stacks sit next to the active memory cells and help guide electrical connections through the layers without interfering with the main data storage area.
In the filing’s own words
A semiconductor device may include a peripheral circuit structure including cell region and an outside region, a cell structure on the cell region, an outside structure on the outside region, and an insulating layer. The outside structure may include a dummy stacked structure, a through electrode penetrating the dummy stacked structure and connected to the peripheral circuit structure, and a dummy vertical structure adjacent to the through electrode and penetrating at least a portion of the dummy stacked structure. The insulating layer may be between the dummy stacked structure and the peripheral circuit structure. The dummy stacked structure may include an upper dummy stacked structure on a lower dummy stacked structure. The upper dummy stacked structure may include upper dummy patterns stacked on the lower dummy stacked structure. The lower dummy stacked structure may include lower dummy patterns stacked on the outside region.
What exactly they claim (claim 1)
1. A semiconductor device comprising: a peripheral circuit structure including a cell region and an outside region; a cell structure on the cell region of the peripheral circuit structure; an outside structure on the outside region of the peripheral circuit structure; and an insulating layer on the peripheral circuit structure, wherein the cell structure includes an electrode structure including electrodes alternately arranged on the cell region, a channel structure penetrating the electrode structure, a conductive pattern connected to the channel structure, an upper horizontal electrode on the electrode structure and the conductive pattern, and an upper semiconductor pattern penetrating the upper horizontal electrode and connected to the conductive pattern, the outside structure includes a dummy stacked structure, a through electrode penetrating the dummy stacked structure and connected to the peripheral circuit structure, and a dummy vertical structure adjacent to the through electrode and penetrating at least a portion of the dummy stacked structure, the dummy stacked structure includes an upper dummy stacked structure on a lower dummy stacked structure, the upper dummy stacked structure includes upper dummy patterns stacked on the lower dummy stacked structure, the lower dummy stacked structure includes lower dummy patterns stacked on the outside region, the insulating layer between the dummy stacked structure and the peripheral circuit structure, and at least a portion of the insulating layer is between the dummy vertical structure and the peripheral circuit structure, wherein an upper surface of the dummy vertical structure has a rounded shape in a plan view.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- Semiconductor device including dummy stacked structure and electronic system including the same
- Patent number
- US12757403B2
- Application number
- 18357401
- Filed
- Jul 24, 2023
- Granted
- Oct 6, 2026
- Inventors
- 2
- Claims
- 20
Classified under
H10B 43/50 Electricity & electronicsH10B 43/27 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.