Samsung patents 3D memory design with backside wiring
Samsung describes a 3D memory chip where the storage cells are stacked above the control circuits, with a new layer of wiring added to the back of the stack. This structure uses specific vertical connections to link the backside wiring to the internal gate electrodes and middle circuits.
In the filing’s own words
Disclosed is a semiconductor device comprising a peripheral circuit structure on a first substrate, a cell array structure on the peripheral circuit structure, and a backside structure on the cell array structure. The cell array structure includes a stack structure including gate electrodes and interlayer dielectric layers that are alternately stacked, through plugs that extend in a first direction through the stack structure and each including a first surface adjacent to the backside structure and a second surface opposite to the first surface, a middle circuit structure between the stack structure and the peripheral circuit structure and connected to the peripheral circuit structure, and a connection plug connected to the middle circuit structure and the backside structure. The through plugs include a first through plug connected through the first surface to the backside structure, and a second through plug connected through the second surface to the middle circuit structure.
What exactly they claim (claim 1)
1. A three-dimensional semiconductor memory device, comprising: a peripheral circuit structure on a first substrate; a cell array structure on the peripheral circuit structure; and a backside structure on the cell array structure; wherein the cell array structure includes: a stack structure including gate electrodes and interlayer dielectric layers that are alternately stacked along a first direction; through plugs that extend in the first direction through the stack structure, each of the through plugs including a first surface adjacent to the backside structure and a second surface opposite to the first surface; a middle circuit structure between the stack structure and the peripheral circuit structure, the middle circuit structure being electrically connected to the peripheral circuit structure; and a connection plug electrically connected to the middle circuit structure and the backside structure, wherein the through plugs include: a first through plug electrically connected through the first surface to the backside structure; and a second through plug electrically connected through the second surface to the middle circuit structure, and at least one of (i) the first through plug is electrically connected to a first pad portion of a first gate electrode of the gate electrodes or (ii) the second through plug is electrically connected to a second pad portion of a second gate electrode of the gate electrodes.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- Three-dimensional semiconductor memory device, electronic system including the same, and method of fabricating the same
- Patent number
- US12757402B2
- Application number
- 18118776
- Filed
- Mar 8, 2023
- Granted
- Oct 6, 2026
- Inventors
- 5
- Claims
- 20
Classified under
H10B 43/40 Electricity & electronicsH10B 43/10 Electricity & electronicsH10B 43/27 Electricity & electronicsH10B 43/35 Electricity & electronicsH10W 20/42 Electricity & electronicsH10W 20/435 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.