Samsung patents 3D memory design to prevent electrical shorts in stacked chips
Samsung has been granted a patent for a specific layout in 3D semiconductor memory chips that uses insulating pads to separate contact plugs from vertical channel structures. This design helps manage the 'bridge pattern' effect, which can cause unwanted electrical connections in densely stacked memory layers.
In the filing’s own words
A three-dimensional semiconductor memory device includes a substrate including a first region and a second region, the second region extending from the first region; a stack including interlayer insulating layers and gate electrodes, which are alternately and repeatedly stacked on the substrate, the stack having a staircase structure on the second region; an insulating layer covering the staircase structure of the stack; first vertical channel structures on the first region, penetrating the stack, and in contact with the substrate; first contact plugs on the second region and penetrating the insulating layer and the stack; and first insulating pads in the insulating layer and enclosing upper portions of the first contact plugs, respectively, wherein the first insulating pads overlap with the first vertical channel structures in a horizontal direction.
What exactly they claim (claim 1)
1. A three-dimensional semiconductor memory device, comprising: a substrate including a first region and a second region, the second region extending from the first region; a stack including interlayer insulating layers and gate electrodes, which are alternately and repeatedly stacked on the substrate, the stack having a staircase structure on the second region; an insulating layer covering the staircase structure of the stack; first vertical channel structures on the first region, penetrating the stack, and in contact with the substrate; first contact plugs on the second region and penetrating the insulating layer and the stack; and first insulating pads in the insulating layer and enclosing upper portions of the first contact plugs, respectively, wherein the first insulating pads are formed of an insulating material that is different from an insulating material of the insulating layer, and outer surfaces of the first insulating pads are in contact with respective inner surfaces of the insulating layer, wherein the first insulating pads overlap with the first vertical channel structures in a horizontal direction.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- Three-dimensional semiconductor memory device with bridge pattern suppression and electronic system including the same
- Patent number
- US12757398B2
- Application number
- 18080325
- Filed
- Dec 13, 2022
- Granted
- Oct 6, 2026
- Inventors
- 3
- Claims
- 20
Classified under
H10B 43/27 Electricity & electronicsH10B 43/40 Electricity & electronicsH10W 20/20 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.