Samsung patents memory chip design using indium, gallium, and tin
Samsung describes a semiconductor memory device that uses vertical channel transistors made from a metal oxide containing indium, gallium, and tin. The design arranges multiple word lines between channel patterns to improve integration and electrical performance.
In the filing’s own words
There is provided a semiconductor memory device having improved integration and electrical characteristics. The semiconductor memory device includes a bit line extending in a first direction on a substrate, a first channel pattern disposed on the bit line, a second channel pattern disposed on the bit line and spaced apart from the first channel pattern in the first direction, a first word line disposed between the first channel pattern and the second channel pattern extends in a second direction, a second word line disposed between the first channel pattern and the second channel pattern, extends in the second direction, and is spaced apart from the first word line in the first direction, and a first capacitor and a second capacitor disposed on and connected to the first channel pattern and the second channel pattern, respectively, wherein each of the first channel pattern and the second channel pattern includes a first metal oxide pattern including indium (In), gallium (Ga) and tin (Sn), and a position of a peak of tin is different from a position of a peak of gallium in a spatial composition distribution of the first metal oxide pattern.
What exactly they claim (claim 1)
1. A semiconductor memory device comprising: a bit line extending in a first direction on a substrate; a first channel pattern disposed on the bit line; a second channel pattern disposed on the bit line and spaced apart from the first channel pattern in the first direction; a first word line disposed between the first channel pattern and the second channel pattern and extending in a second direction; a second word line disposed between the first channel pattern and the second channel pattern, extending in the second direction and is spaced apart from the first word line in the first direction; and a first capacitor and a second capacitor disposed on and connected to the first channel pattern and the second channel pattern, respectively, wherein each of the first channel pattern and the second channel pattern includes a first metal oxide pattern including indium (In), gallium (Ga), and tin (Sn), and a position of a peak of tin is different from a position of a peak of gallium in a spatial composition distribution of the first metal oxide pattern.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- Semiconductor memory device with vertical channel transistors including multiple word lines
- Patent number
- US12757379B2
- Application number
- 18493924
- Filed
- Oct 25, 2023
- Granted
- Oct 6, 2026
- Inventors
- 7
- Claims
- 20
Classified under
H10B 12/315 Electricity & electronicsH10B 12/05 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.