Samsung patents memory chip layout with uneven protective caps
This patent describes a specific physical layout for semiconductor memory chips. It details how protective layers, or capping patterns, are placed over electrical connections in the center and edges of the chip, with the center layer sitting higher than the edge layer.
In the filing’s own words
A semiconductor memory device includes a substrate including a memory cell region, a first bit line on a center region of the memory cell region, a first landing pad on the first bit line, a first bit line capping pattern between the first bit line and first landing pad, a second bit line on an edge region of the memory cell region, a second landing pad on the second bit line, and a second bit line capping pattern between the second bit line and the second landing pad. The first and second bit line capping patterns vertically overlap the first and second landing pads, respectively. A distance from the top of the first bit line capping pattern from the top of the first landing pad is greater than a distance from the top of the second bit line capping pattern to from the top of the second landing pad.
What exactly they claim (claim 1)
1. A semiconductor memory device comprising: a substrate including a memory cell region, the memory cell region including a cell center region and a cell edge region surrounding the cell center region; a first bit line on the cell center region; a first landing pad on the first bit line; a first bit line capping pattern between the first bit line and the first landing pad; a second bit line on the cell edge region; a second landing pad on the second bit line; and a second bit line capping pattern between the second bit line and the second landing pad, wherein the first bit line capping pattern vertically overlaps the first landing pad, the second bit line capping pattern vertically overlaps the second landing pad, and a first distance from an upper surface of the first bit line capping pattern to an upper surface of the first landing pad is greater than a second distance from an upper surface of the second bit line capping pattern to an upper surface of the second landing pad.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- Semiconductor memory device
- Patent number
- US12757378B2
- Application number
- 18432290
- Filed
- Feb 5, 2024
- Granted
- Oct 6, 2026
- Inventors
- 3
- Claims
- 20
Classified under
H10B 12/315 Electricity & electronicsH10B 12/02 Electricity & electronicsH10B 12/482 Electricity & electronicsH10B 12/50 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.