Microsoft patents chip design that doubles data speed inside processors
Microsoft has been granted a patent for a method to send data twice as fast through the internal wiring of a computer chip. The design uses specific timing circuits to capture and forward data on both the rising and falling edges of the clock signal, effectively doubling the bandwidth without changing the physical wire speed.
In the filing’s own words
Double-data rate (DDR) transmission within a system-on-chip (SoC) via network-on-chip (NOC) interconnects is described. A method for transmitting data includes a local programmable delay circuit receiving a source synchronous clock (SSC) signal and outputting a delayed source synchronous clock (SSC) signal. The method further includes a local pulse generator, associated with a first NOC interconnect stage, receiving the delayed SSC signal and generating a first pulse in response to a first phase of the delayed SSC signal and generating a second pulse in response to a second phase of the delayed SSC signal. The method further includes a flop-repeater circuit, associated with the first NOC interconnect stage, capturing and launching data received from the source circuit in response to each of the first pulse and the second pulse. The method further includes a local offset circuit receiving the delayed SSC signal and providing a de-skewed SSC signal.
What exactly they claim (claim 1)
1. A network-on-chip (NOC) interconnect for transmitting data from a source circuit to a sink circuit, wherein the NOC interconnect is clocked using a source synchronous clock signal, the NOC interconnect comprising: a first NOC interconnect stage, to receive data from the source circuit, comprising: (1) a local programmable delay circuit to receive the source synchronous clock signal and output a delayed source synchronous clock signal, (2) a local pulse generator configured to receive the delayed source synchronous clock signal and generate a first pulse in response to a first phase of the delayed source synchronous clock signal and generate a second pulse in response to a second phase of the delayed source synchronous clock signal, (3) a flop-repeater circuit to both capture and launch data received from the source circuit in response to each of the first pulse and the second pulse, and (4) a local offset circuit, wherein the local offset circuit is configured to receive the delayed source synchronous clock signal and provide a de-skewed source synchronous clock signal; and a second NOC interconnect stage to receive the launched data from the flop-repeater circuit and the de-skewed source synchronous clock signal from the local offset circuit.
Facts
- Company
- Microsoft (Microsoft Technology Licensing, LLC)
- Official title
- Double-data rate transmission within a system-on-chip via network-on-chip interconnects
- Patent number
- US12756532B2
- Application number
- 18924572
- Filed
- Oct 23, 2024
- Granted
- Oct 6, 2026
- Inventors
- 3
- Claims
- 20
Classified under
H04L 7/0008 Electricity & electronicsG06F 1/10 Physics & computingH03K 5/06 Electricity & electronicsH03K 5/14 Electricity & electronicsMore from Microsoft in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.